Cache-related problem in some STM32 HAL drivers

[Giovanni]

Hi,

Putting this here to keep track.

Several LLDs have DMA-accessible buffers inside the driver structure, this is a problem on those devices where cache coherency must be handled.

Required action: move all buffers outside the driver structure, replace those with a pointer to the actual buffer which should be aligned to cache lines.

Giovanni

[Giovanni]

bump

[faisal]

Has this been addressed? If so, in what versions?

[Giovanni]

This has been addressed for SNOR, now XSNOR. I need to check sd_mmc but I think it was addressed there too.

Giovanni

[FXCoder]

Addressed the SPI dummy variables as well by allowing the entire driver structure to be located in non-cache.
Drivers now have this for allocation...

Code: Select all

/** @brief SPI1 driver identifier.*/
#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
SPI_SPID1_MEMORY SPIDriver SPID1;
#endif

So just define the non-cache section to be used.