Index: hal_adc_lld.c
===================================================================
--- hal_adc_lld.c	(revision 14054)
+++ hal_adc_lld.c	(working copy)
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -138,7 +138,7 @@
 }
 
 /**
- * @brief   Disables the ADC  analog circuit.
+ * @brief   Disables the ADC analog circuit.
  *
  * @param[in] adcp      pointer to the @p ADCDriver object
  */
@@ -308,18 +308,22 @@
  * @isr
  */
 OSAL_IRQ_HANDLER(STM32_ADC12_HANDLER) {
+
   uint32_t isr;
 
   OSAL_IRQ_PROLOGUE();
+  /* Handle ADC1 ISR first in adc_lld_serve_interrupt. */
+  isr  = ADC1->ISR;
+  ADC1->ISR = isr;
+#if defined(STM32_ADC_ADC12_IRQ_HOOK)
+  STM32_ADC_ADC12_IRQ_HOOK
+#endif
+  adc_lld_serve_interrupt(&ADCD1, isr);
 
-  isr  = ADC1->ISR;
+  /* Handle ADC2 ISR next in adc_lld_serve_interrupt. */
 #if STM32_ADC_DUAL_MODE
   isr |= ADC2->ISR;
-#endif
-  ADC1->ISR = isr;
-#if STM32_ADC_DUAL_MODE
   ADC2->ISR = isr;
-#endif
 #if defined(STM32_ADC_ADC12_IRQ_HOOK)
   STM32_ADC_ADC12_IRQ_HOOK
 #endif
@@ -620,51 +624,64 @@
   }
 #endif /* STM32_ADC_USE_ADC3 == TRUE */
 
-  /* ADC setup, if it is defined a callback for the analog watch dog then it
-     is enabled.*/
+  /* If a callback is set enable the overflow and analog watch dog interrupts. */
   adcp->adcm->ISR   = adcp->adcm->ISR;
-  adcp->adcm->IER   = ADC_IER_OVRIE | ADC_IER_AWD1IE;
+  if (grpp->error_cb != NULL) {
+  adcp->adcm->IER   = ADC_IER_OVRIE | ADC_IER_AWD1IE
+  																	| ADC_IER_AWD2IE
+  																	| ADC_IER_AWD3IE;
+  }
 #if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE
   /* Configuration for dual mode ADC12 */
   if (&ADCD1 == adcp) {
+    /* If a callback is set enable the overflow and analog watch dog interrupts. */
+    adcp->adsm->ISR   = adcp->adsm->ISR;
+    if (grpp->error_cb != NULL) {
+    adcp->adsm->IER   = ADC_IER_OVRIE | ADC_IER_AWD1IE
+                                      | ADC_IER_AWD2IE
+                                      | ADC_IER_AWD3IE;
     /* Configuring the CCR register with the user-specified settings
       in the conversion group configuration structure, static settings are
       preserved.*/
-    adcp->adcc->CCR   = (adcp->adcc->CCR &
-                        (ADC_CCR_CKMODE_MASK | ADC_CCR_DAMDF_MASK)) | ccr;
+    adcp->adcc->CCR     = (adcp->adcc->CCR &
+                          (ADC_CCR_CKMODE_MASK | ADC_CCR_DAMDF_MASK)) | ccr;
 
-    adcp->adcm->CFGR2 = grpp->cfgr2;
-    adcp->adcm->PCSEL = grpp->pcsel;
-    adcp->adcm->LTR1  = grpp->ltr1;
-    adcp->adcm->HTR1  = grpp->htr1;
-    adcp->adcm->LTR1  = grpp->ltr2;
-    adcp->adcm->HTR1  = grpp->htr2;
-    adcp->adcm->LTR1  = grpp->ltr3;
-    adcp->adcm->HTR1  = grpp->htr3;
-    adcp->adcm->SMPR1 = grpp->smpr[0];
-    adcp->adcm->SMPR2 = grpp->smpr[1];
-    adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
-    adcp->adcm->SQR2  = grpp->sqr[1];
-    adcp->adcm->SQR3  = grpp->sqr[2];
-    adcp->adcm->SQR4  = grpp->sqr[3];
-    adcp->adcs->CFGR2 = grpp->cfgr2;
-    adcp->adcs->PCSEL = grpp->pcsel;
-    adcp->adcs->LTR1  = grpp->ltr1;
-    adcp->adcs->HTR1  = grpp->htr1;
-    adcp->adcs->LTR1  = grpp->ltr2;
-    adcp->adcs->HTR1  = grpp->htr2;
-    adcp->adcs->LTR1  = grpp->ltr3;
-    adcp->adcs->HTR1  = grpp->htr3;
-    adcp->adcs->SMPR1 = grpp->ssmpr[0];
-    adcp->adcs->SMPR2 = grpp->ssmpr[1];
-    adcp->adcs->SQR1  = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
-    adcp->adcs->SQR2  = grpp->ssqr[1];
-    adcp->adcs->SQR3  = grpp->ssqr[2];
-    adcp->adcs->SQR4  = grpp->ssqr[3];
+    adcp->adcm->CFGR2   = grpp->cfgr2;
+    adcp->adcm->PCSEL   = grpp->pcsel;
+    adcp->adcm->LTR1    = grpp->ltr1;
+    adcp->adcm->HTR1    = grpp->htr1;
+    adcp->adcm->LTR2    = grpp->ltr2;
+    adcp->adcm->HTR2    = grpp->htr2;
+    adcp->adcm->LTR3    = grpp->ltr3;
+    adcp->adcm->HTR3    = grpp->htr3;
+    adcp->adcm->AWD2CR  = grpp->awd2cr;
+    adcp->adcm->AWD2CR  = grpp->awd3cr;
+    adcp->adcm->SMPR1   = grpp->smpr[0];
+    adcp->adcm->SMPR2   = grpp->smpr[1];
+    adcp->adcm->SQR1    = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
+    adcp->adcm->SQR2    = grpp->sqr[1];
+    adcp->adcm->SQR3    = grpp->sqr[2];
+    adcp->adcm->SQR4    = grpp->sqr[3];
+    adcp->adcs->CFGR2   = grpp->cfgr2;
+    adcp->adcs->PCSEL   = grpp->pcsel;
+    adcp->adcs->LTR1    = grpp->sltr1;
+    adcp->adcs->HTR1    = grpp->shtr1;
+    adcp->adcs->LTR1    = grpp->sltr2;
+    adcp->adcs->HTR1    = grpp->shtr2;
+    adcp->adcs->LTR1    = grpp->sltr3;
+    adcp->adcs->HTR1    = grpp->shtr3;
+    adcp->adcs->AWD2CR  = grpp->sawd2cr;
+    adcp->adcs->AWD3CR  = grpp->sawd3cr;
+    adcp->adcs->SMPR1   = grpp->ssmpr[0];
+    adcp->adcs->SMPR2   = grpp->ssmpr[1];
+    adcp->adcs->SQR1    = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
+    adcp->adcs->SQR2    = grpp->ssqr[1];
+    adcp->adcs->SQR3    = grpp->ssqr[2];
+    adcp->adcs->SQR4    = grpp->ssqr[3];
 
     /* ADC configuration.*/
-    adcp->adcm->CFGR  = cfgr;
-    adcp->adcs->CFGR  = cfgr;
+    adcp->adcm->CFGR    = cfgr;
+    adcp->adcs->CFGR    = cfgr;
   }
 
 #endif /* STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC12 == TRUE */
@@ -671,28 +688,25 @@
 
 #if STM32_ADC_DUAL_MODE == FALSE || STM32_ADC_USE_ADC3 == TRUE
   /* Configuration for ADC3 and single mode ADC1 */
-#if STM32_ADC_DUAL_MODE == TRUE && STM32_ADC_USE_ADC3 == TRUE
-  if (&ADCD3 == adcp)
-#endif
-  {
-    adcp->adcm->CFGR2 = grpp->cfgr2;
-    adcp->adcm->PCSEL = grpp->pcsel;
-    adcp->adcm->LTR1  = grpp->ltr1;
-    adcp->adcm->HTR1  = grpp->htr1;
-    adcp->adcm->LTR1  = grpp->ltr2;
-    adcp->adcm->HTR1  = grpp->htr2;
-    adcp->adcm->LTR1  = grpp->ltr3;
-    adcp->adcm->HTR1  = grpp->htr3;
-    adcp->adcm->SMPR1 = grpp->smpr[0];
-    adcp->adcm->SMPR2 = grpp->smpr[1];
-    adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
-    adcp->adcm->SQR2  = grpp->sqr[1];
-    adcp->adcm->SQR3  = grpp->sqr[2];
-    adcp->adcm->SQR4  = grpp->sqr[3];
+    adcp->adcm->CFGR2   = grpp->cfgr2;
+    adcp->adcm->PCSEL   = grpp->pcsel;
+    adcp->adcm->LTR1    = grpp->ltr1;
+    adcp->adcm->HTR1    = grpp->htr1;
+    adcp->adcm->LTR1    = grpp->ltr2;
+    adcp->adcm->HTR1    = grpp->htr2;
+    adcp->adcm->LTR1    = grpp->ltr3;
+    adcp->adcm->HTR1    = grpp->htr3;
+    adcp->adcm->AWD2CR  = grpp->awd2cr;
+    adcp->adcm->AWD3CR  = grpp->awd3cr;
+    adcp->adcm->SMPR1   = grpp->smpr[0];
+    adcp->adcm->SMPR2   = grpp->smpr[1];
+    adcp->adcm->SQR1    = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
+    adcp->adcm->SQR2    = grpp->sqr[1];
+    adcp->adcm->SQR3    = grpp->sqr[2];
+    adcp->adcm->SQR4    = grpp->sqr[3];
 
     /* ADC configuration.*/
     adcp->adcm->CFGR  = cfgr;
-  }
 #endif
 
   /* Starting conversion.*/
Index: hal_adc_lld.h
===================================================================
--- hal_adc_lld.h	(revision 14054)
+++ hal_adc_lld.h	(working copy)
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -600,10 +600,26 @@
   uint32_t                  ltr3;                                           \
   /* ADC HTR3 register initialization data.*/                               \
   uint32_t                  htr3;                                           \
+  /* ADC AWD2CR register initialization data.*/                             \
+  uint32_t									awdcr2;                                         \
+  /* ADC AWD3CR register initialization data.*/                             \
+  uint32_t									awdcr3;                                         \
   /* ADC SMPRx registers initialization data.*/                             \
   uint32_t                  smpr[2];                                        \
   /* ADC SQRx register initialization data.*/                               \
   uint32_t                  sqr[4];                                         \
+  /* Slave ADC LTR/HTRx registers initialization data.                      \
+     NOTE: This field is only present in dual mode.*/                       \
+  uint32_t                  sltr1;                                          \
+  uint32_t                  shtr1;                                          \
+  uint32_t                  sltr2;                                          \
+  uint32_t                  shtr2;                                          \
+  uint32_t                  sltr3;                                          \
+  uint32_t                  shtr3;                                          \
+  /* Slave ADC AWDCRx registers initialization data.                        \
+     NOTE: This field is only present in dual mode.*/                       \
+  uint32_t                  sawdcr2;                                        \
+  uint32_t                  sawdcr3;                                        \
   /* Slave ADC SMPRx registers initialization data.                         \
      NOTE: This field is only present in dual mode.*/                       \
   uint32_t                  ssmpr[2];                                       \
@@ -622,6 +638,8 @@
   uint32_t                  htr2;                                           \
   uint32_t                  ltr3;                                           \
   uint32_t                  htr3;                                           \
+  uint32_t                  awdcr2;                                         \
+  uint32_t                  awdcr3;                                         \
   uint32_t                  smpr[2];                                        \
   uint32_t                  sqr[4]
 #endif /* STM32_ADC_DUAL_MODE == FALSE */
