What rew said makes sense and is what i am expecting. Using the UART demo in testhal,
Changing to use:
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLMUL_VALUE 4
Gave me a faster delay than:
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLMUL_VALUE 9
Can someone explain ...
Search found 6 matches
- Sun Feb 14, 2016 1:00 am
- Forum: STM32 Support
- Topic: delay changes with clock settings?
- Replies: 7
- Views: 3849
- Sat Feb 13, 2016 3:25 pm
- Forum: STM32 Support
- Topic: delay changes with clock settings?
- Replies: 7
- Views: 3849
Re: delay changes with clock settings?
My HSE is 8Mhz which is the same as the internal RC.
How about question 2 and 3? Why is chThdSleepMilliseconds() affected by clock settings? Should it not be independent of this setting?
Also, a lower STM32_PLLMUL_VALUE give me a slower clock, hence a longer delay instead of something faster ...
How about question 2 and 3? Why is chThdSleepMilliseconds() affected by clock settings? Should it not be independent of this setting?
Also, a lower STM32_PLLMUL_VALUE give me a slower clock, hence a longer delay instead of something faster ...
- Sat Feb 13, 2016 2:18 pm
- Forum: STM32 Support
- Topic: delay changes with clock settings?
- Replies: 7
- Views: 3849
delay changes with clock settings?
I am using the default files from testhal/UART for STM32F103 and having some difficulty understanding how this works. on ChibiOS 3.0.0
1.) The default demo should provide a system clock frequency of 72Mhz right?
2.) Changing STM32_PLLSRC to STM32_PLLSRC_HSI, the delay seems to be doubled
while ...
1.) The default demo should provide a system clock frequency of 72Mhz right?
2.) Changing STM32_PLLSRC to STM32_PLLSRC_HSI, the delay seems to be doubled
while ...
- Thu Feb 11, 2016 7:11 pm
- Forum: General Support
- Topic: translate Delay() to chibios 3.0
- Replies: 9
- Views: 6295
Re: translate Delay() to chibios 3.0
I cannot find `US2RT()` are you able to point me to the correct file? The compiler throws an error as well when i use it.
Would appreciate if you can point out any incorrect settings for the clock frequency - https://github.com/kennethlimcp/ChibiOS ... /mcuconf.h
Would appreciate if you can point out any incorrect settings for the clock frequency - https://github.com/kennethlimcp/ChibiOS ... /mcuconf.h
- Thu Feb 11, 2016 6:44 pm
- Forum: General Support
- Topic: translate Delay() to chibios 3.0
- Replies: 9
- Views: 6295
Re: translate Delay() to chibios 3.0
Code: Select all
while(TRUE){
palWritePad(GPIOC, GPIOC_EINK_CKV, TRUE);
chSysPolledDelayX(US2ST(5));
palWritePad(GPIOC, GPIOC_EINK_CKV, FALSE);
chSysPolledDelayX(US2ST(5));
}
Opps my typo. Should be `US2ST()`?
I did this but the logic analyzer shows a waveform of 0.25us delay..
- Thu Feb 11, 2016 4:45 pm
- Forum: General Support
- Topic: translate Delay() to chibios 3.0
- Replies: 9
- Views: 6295
Re: translate Delay() to chibios 3.0
Hey Giovanni,
Do i use US2RT() for chSysPolledDelayX()? If not, what should be the correct way to use chSysPolledDelayX() to create microsecond delays?
Thanks!
ken
Do i use US2RT() for chSysPolledDelayX()? If not, what should be the correct way to use chSysPolledDelayX() to create microsecond delays?
Thanks!
ken