ChibiOS Free Embedded RTOS

Hi,
I have some small fixes for the RCC changes, CAN and RCC CRC config for stm32f373.

regards
Nicolas

Fine.
Thank you.

Nicolas

what is the point in keeping clocks enabled in sleep mode and disabled in run mode?

Did you mean what is the point in keeping clocks disabled in sleep mode and enabled in run mode?

The Problem is that the CPU puts a message to the mailbox, goes to sleep and the CAN block clock gets switched off ...

Hello Giovanni,
the change to remove lowpower config from RCC clockdisable macros e.g. leads to a non working can interface.

From RM0385

RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0xFFFF CBFFh

So the default is that all hardware ...

Hi Giovanni,

I have some small fixes, cleanup and enhancements to the HAL.

Regards
Nicolas

Patched generator files.

The default is "Low driving capability" and can cause problems like clock-jitter and very unprecise time.

There are two bugs in the sdmmc commit.
in addition I add the patches which are not commited.

1: fix warning when compiling SHELL_USE_COMPLETION TRUE
2: STM32F4xx/stm32_registry.h: fix wrong OTG endpoint count
3: STM32/LLD/SDMMCv1/hal_sdc_lld.c: disable clock while idle (pwrsav)
4: fix doku / codestyle

Hi

the STM32F7 HAL is missing the code to set the LSEDRV bits.

Hi,

the commit is missing one character in EXTI and xWDG path

PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/WDGv1/hal_wdg_lld.c
-> PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
...
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTv1/hal_ext_lld.c
->PLATFORMSRC ...