ChibiOS Free Embedded RTOS

I found this :
DTCM-RAM not accessible in read when the MCU is in Sleep mode (WFI/WFE)

Description
• The DTCM-RAM is not accessible in read during Sleep mode (when the CPU clock is
gated). When a read access to the DTCM-RAM is performed by an AHB bus master
(that are the DMAs) while the CPU is in ...

Hello,

I did but as DTCM is never cached, how could it affect it ?

Thank you for the answer.

Somewhat related question : I had ICache and DCache completely disabled. I had a DMA buffer in RAM3 for SDMMC1 aligned to 32 bytes. It did unaligned read sometimes. It worked fine. I re-enabled ICache/DCache and things went wrong when the reads where unaligned. How is this ...

Hello, if cache invalidation for DMA is handled by the user, are there any issues or disadvantages to merge the ram3 zone with ram1 and ram2 into a contiguous ram0 ?

From : ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
ram1 : org = 0x20020000, len = 368k /* SRAM1 */
ram2 : org ...