Hi,
The OTGv1 driver for STM32 is missing a semicolon which breaks the build if ULPI is enabled. The attached patch fixes the problem
regards
christian
Search found 4 matches
- Tue Sep 27, 2022 7:15 pm
- Forum: Bug Reports
- Topic: [patch] STM32/OTGv1: syntax error if ULPI is enabled
- Replies: 1
- Views: 2937
- Tue Mar 16, 2021 9:23 pm
- Forum: Small Change Requests
- Topic: STM32H7xx SRAM4 no-cache option
- Replies: 0
- Views: 6759
STM32H7xx SRAM4 no-cache option
Hi,
Since the BDMA controller on STM32H7xx can only reach SRAM4 it would be great to have an easy way to disable caching for this region using a simple define at mcuconf.h. Very much like they are available for SRAM1, SRAM2 and SRAM3. Especially since talking to SRAM4 is very inefficient for most ...
Since the BDMA controller on STM32H7xx can only reach SRAM4 it would be great to have an easy way to disable caching for this region using a simple define at mcuconf.h. Very much like they are available for SRAM1, SRAM2 and SRAM3. Especially since talking to SRAM4 is very inefficient for most ...
- Tue Mar 16, 2021 9:07 pm
- Forum: Bug Reports
- Topic: BDMA double buffer mode on STM32H7xx Rev. Y
- Replies: 3
- Views: 4805
BDMA double buffer mode on STM32H7xx Rev. Y
Hi,
I'm currently working on a project based on a STM32H743 that needs all 4 SAI units running simultaneously at 48kHz sample rate. Each SAI block has to handle 8 audio samples at 24bit. IMHO the only way to handle this much data is to implement a zero-copy scheme based on the DMA double buffer ...
I'm currently working on a project based on a STM32H743 that needs all 4 SAI units running simultaneously at 48kHz sample rate. Each SAI block has to handle 8 audio samples at 24bit. IMHO the only way to handle this much data is to implement a zero-copy scheme based on the DMA double buffer ...
- Tue Mar 16, 2021 8:26 pm
- Forum: Bug Reports
- Topic: [patch] DMAMUX Macros for SAI are inconsistent on STM32H7xx
- Replies: 3
- Views: 4556
[patch] DMAMUX Macros for SAI are inconsistent on STM32H7xx
Hi,
The names of the DMAMUX request sources for SAI3 and SAI4 use a different naming scheme than SAI1 and SAI2.
STM32_DMAMUX1_SAI1_A vs. STM32_DMAMUX1_SAI3A
The attached patch changes the names for SAI3 and SAI4 to follow the naming scheme of SAI1 and SAI2. Of course i don't really care which ...
The names of the DMAMUX request sources for SAI3 and SAI4 use a different naming scheme than SAI1 and SAI2.
STM32_DMAMUX1_SAI1_A vs. STM32_DMAMUX1_SAI3A
The attached patch changes the names for SAI3 and SAI4 to follow the naming scheme of SAI1 and SAI2. Of course i don't really care which ...