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by faisal
Mon Oct 09, 2017 3:00 pm
Forum: Small Change Requests
Topic: STM32 UART LLD, character match interrupt Topic is solved
Replies: 13
Views: 4907

Re: STM32 UART LLD, character match interrupt Topic is solved

I quite like this feature (as I also use COBS-ZP/ZE). I have an NUCLEO-F7 on the way, I could probably add the missing parts if no one feels up to the task. Cool, check out my example code in the first post. I actually have a ring buffer *of* COBS frames (like 5 framed deep) that the interrupt push...
by faisal
Mon Oct 09, 2017 2:36 pm
Forum: Small Change Requests
Topic: STM32 UART LLD, character match interrupt Topic is solved
Replies: 13
Views: 4907

Re: STM32 UART LLD, character match interrupt Topic is solved

That is a really useful feature! Which MCUs has it? I could only find it on the STM32F7s. Could it still be integrated if it is not a generic feature, Giovanni? Many MCUs support the character match interrupt. Im currently using it on the stm32L4 series. Works like a charm, and is almost necessary ...
by faisal
Fri Oct 06, 2017 9:49 pm
Forum: Small Change Requests
Topic: Guarded Memory pool which allows for dynamic allocation/growth Topic is solved
Replies: 1
Views: 914

Guarded Memory pool which allows for dynamic allocation/growth Topic is solved

#define GUARDEDMEMORYPOOL_DECL(name, size) could also include an allocator, as does MEMORYPOOL_DECL(name, size, provider). But in the case of a guarded memory pool, the size parameter restricts the growth of the memory pool - unlike with a regular memory pool.
by faisal
Fri Oct 06, 2017 9:41 pm
Forum: Small Change Requests
Topic: STM32 UART LLD, character match interrupt Topic is solved
Replies: 13
Views: 4907

STM32 UART LLD, character match interrupt Topic is solved

The character match interrupt is very useful for efficient packetized communications over uart. For example, if you use COBS encoding (https://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing), you can enable the character match interrupt (CR1->CMIE) for a 0 (which is the escaped character in...
by faisal
Mon Oct 02, 2017 10:31 pm
Forum: Small Change Requests
Topic: chEvtAddEvents(), I/S class versions please Topic is solved
Replies: 4
Views: 1649

Re: chEvtAddEvents(), I/S class versions please Topic is solved

Another one: chEvtGetAndClearEvents, I class version please :) . eventmask_t chEvtGetAndClearEventsI(eventmask_t events) { eventmask_t m; m = currp->epending & events; currp->epending &= ~events; return m; } /** * @brief Clears the pending events specified in the events mask. * * @param[in] ...
by faisal
Wed Sep 27, 2017 1:35 am
Forum: Development and Feedback
Topic: [NOTE] Ideas for RT 5 and/or NIL 3
Replies: 11
Views: 5564

Re: [NOTE] Ideas for RT 5 and/or NIL 3

I am introducing a "factory" mechanism for both RT and NIL, it allows to fabricate objects like buffers, semaphores, mutexes, mailboxes etc and give them a name. The objects have a reference counter so the memory is freed when all object users have released their reference. This will allo...
by faisal
Wed Sep 27, 2017 1:30 am
Forum: Development and Feedback
Topic: [NOTE] Ideas for RT 5 and/or NIL 3
Replies: 11
Views: 5564

Re: [NOTE] Ideas for RT 5 and/or NIL 3

Memory pool object chain: Basically a dynamically sizable memory object, which can grow by allocating and appending new memory pool objects to a linked list, and shrink by deallocating memory pool objects and deleting them from the list. This is useful for all sorts of applications. Some helper meth...
by faisal
Mon Sep 25, 2017 5:01 am
Forum: Small Change Requests
Topic: chEvtAddEvents(), I/S class versions please Topic is solved
Replies: 4
Views: 1649

chEvtAddEvents(), I/S class versions please Topic is solved

It would be good to have an S class versions of the chEvtAddEvents function. I usually use it in a context where I'm already in a chSysLock() state.
by faisal
Mon Sep 25, 2017 4:08 am
Forum: Development and Feedback
Topic: GenericQueue with counter?
Replies: 8
Views: 2803

Re: GenericQueue with counter?

Just want to chime in with another vote for lock-less single producer single consumer queues. I was working on a high performance DSP application (on a relatively slow) processor a while back, and lock-less queues saved the day (given the assumption of a single producer, single consumer) along with ...

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