STM32F401: ADC Config,How I get a sampling freq ~100Hz) Topic is solved

[raulvalencia]

Hi everyone,

I'm working with nucleo STM32F401 board and ChibiOS 16.1.3

My question is : how do I configure my ADCConversionGroup to have in channel 0 a sampling frequency = ~100 HZ, I read that we have to set the ADC_SMPR2 register but we have only 3 bits, I mean 8 choices...

Maybe if I use the Timer 3 TRGO event (or another one) to trigger my convert but the number of simples have to be 1?

I was reading that:

11.3.2 ADC clock
The ADC features two clock schemes:
• Clock for the analog circuitry: ADCCLK
This clock is generated from the APB2 clock divided by a programmable prescaler that
allows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the
maximum value of ADCCLK.
• Clock for the digital interface (used for registers read/write access)
This clock is equal to the APB2 clock. The digital interface clock can be
enabled/disabled individually for each ADC through the RCC APB2 peripheral clock
enable register (RCC_APB2ENR).

somebody has any idea ?


Thank you in advance for your help,

Raul

[Giovanni]

Hi,

If you need an accurate sampling rate then you need a GPT timer triggering the ADC via the TRGO signal, look at the GPT-ADC demos under /testhal, there is one for the F7 that can be used as reference for the F4.

Giovanni

[raulvalencia]

Thanks a lot,

I'm going to try that...



Raul

[RoccoMarco]

Hi,
if you are using STM32 Nucleo-64 F401RE I have already ported that demo sometime ago. It should work with 16.1
http://www.playembedded.org/blog/wp-content/uploads/2016/04/RT-STM32F401RE-NUCLEO-GPT-ADC.zip

There are some other demos for that board here
http://www.playembedded.org/blog/en/download/

If you are using STM32F401C Discovery or a custom board you have to port it. Here some info about this procedure:
http://www.playembedded.org/blog/en/2016/05/29/how-to-port-a-chibios-demo/
Ciao,
RM

[raulvalencia]

Thanks!

your website is very interesting...

I'm going to see your demos...

Raul