CAN_BTR_LBKM flag Topic is solved

[hybridA]

Hi,
I'm new to ChibiOS and found some odd behaviour when setting up CAN on my board using an STM32F103VB.
Using stable_21.6.x.
I only got the can bus brought up OK when ORing in the CAN_BTR_LBKM flag into the config.
I thought that would enable loopback mode, but I'm able to send data out the can bus OK. (using a CAN recorder via USB on the other end)
Is this the expected behaviour or am I missing something?

Thanks,
James

[Giovanni]

Hi,

It is for loopback, probably you are able to send data but would not be able to receive it. I would check GPIO, AFIO and SYSCONF settings.

This is not a driver behavior, it as about how HW works.

Giovanni

[hybridA]

Thanks Giovanni, yes I got thrown off by the fact that this flag made it work.
I looked through my config files, can't seem to find anything obvious.
CAN RX is connected PA11
CAN TX is connected to PA12
/*
* IO pins assignments.
*/
#define GPIOA_ARD_A0 0U
#define GPIOA_ADC1_IN0 0U
#define GPIOA_ARD_A1 1U
#define GPIOA_ADC1_IN1 1U
#define GPIOA_ARD_D1 2U
#define GPIOA_USART2_TX 2U
#define GPIOA_ARD_D0 3U
#define GPIOA_USART2_RX 3U
#define GPIOA_ARD_A2 4U
#define GPIOA_ADC1_IN4 4U
#define GPIOA_LED_GREEN 5U
#define GPIOA_ARD_D13 5U
#define GPIOA_ARD_D12 6U
#define GPIOA_ARD_D11 7U
#define GPIOA_ARD_D7 8U
#define GPIOA_ARD_D8 9U
#define GPIOA_ARD_D2 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_SWDIO 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U

#define VAL_GPIOACRH 0x888B88B2 /* PA15...PA8 */

CAN is enabled in mcuconf.h

thank you

[Giovanni]

Is the CAN baud rate the one you expect? this could be the reason you are not receiving data.

Also check in AFIO that CAN is not remapped.

Giovanni

[hybridA]

Yes the baud rate is correct.
I have the bus on the scope at the same time, to check if there is any communication.
Is there an easy way to check if AFIO is being remapped somewhere? Or would I have to dig through my includes?

Thanks,
James

[Giovanni]

Hi, you need to inspect the registers looking at the reference manual. The register should be OK unless something initialized it (the HAL does not touch it).

Giovanni

[hybridA]

I was able to verify that while in loopback mode, the STM transmits CAN for verification purposes, so that is indeed expected behaviour.

looking at it on a register level, I was able to see that AFIO are configured correctly and CAN is enabled.

I noticed ERRI in CAN_MSR is set, indicating an error status. It remained unset when configured in loopback mode.
TERR0 in CAN_TSR was set as well showing a previous failed transmission due to an error.
Looking at the CAN_IER register i can see ERRI set, indicating a pending error condition in the CAN_ESR.

CAN_ESR has following bits set:
EWGF (warning limit has been reached)
BOFF (Bus off flag)
LEC: 101 Bit dominant Error
REC: 0x2A (not trying to receive messages in my sample code, I guess this can be ignored)

I'm not exactly sure what 'bit dominant error' means. My bus is <10 inches long and properly terminated on both ends.
I have an older version of my application (written with libopencm3), which works fine on the exact same hardware.
ERRI in the CAN_MSR register is not set when running the older (libopencm3) firmware.

Thank you,
James

[Giovanni]

Hi,

Dominant error can mean that the bus is kept at a fixed level. In my opinion there is some problem with GPIO settings or HW (wiring, driver).

Giovanni