STM32H7 Silicon errata for SPI peripheral

[dynfer]

The STM32H7 suffers a silicon bug in the SPI peripheral which results in a garbage byte being read by the peripheral when using DMA.
The ST Errata sheet provides a workaround for this issue in the form of a reset of the peripheral before continuing.

We got a proof of concept fix for the issue below

https://github.com/FOME-Tech/ChibiOS/co ... 8812f52fe7

https://github.com/ChibiOS/ChibiOS/comm ... e45be30b24

[mck1117]

We do it there before a send as well, but I'm pretty sure it's only required before receive or exchange (and should get moved to the spi lld).

[FXCoder]

Hi,
The errata states that issue occurs only after a simplex SPI transmission.
ChibiOS SPIv3 driver uses duplex for send and receive with DMA (the receive side acts to terminate a send transaction).
For polled a simple direct write of transmit register is followed by waiting on receive.

So it seems this errata should not apply to ChibiOS SPIv3 (unless there is external use of SPI doing a simplex transmission independently).

--
Bob

[mck1117]

The unmodified SPI MMC driver runs in to this on H7. Here's the github issue where I debugged it and followed it back to the errata sheet: https://github.com/rusefi/rusefi/issues ... -785337711

[mck1117]

If I had to guess, that means the bug isn't exactly "simplex TX followed by DMA RX" but is actually something like "any operation without RX MINC set, followed by an operation with RX MINC set"

[Giovanni]

Hi,

So, you are running the plain SPI driver and you are still affected by the errata?

I think "RX MINC" is a DMA-level thing, why should the SPI be affected by that?

Giovanni

[Giovanni]

Probably the best approach would be creating a very simple test applications, using just SPI functions, triggering the problem.

Giovanni