Where to start STM32H7 support

[andypiper]

Hi,

No need to struggle too much, in mcuconf.h there is this:

Code: Select all

/*
 * Memory attributes settings.
 */
#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
#define STM32_NOCACHE_SRAM3                 TRUE


The related code is in hal_lld.c, you can use that as example.

Giovanni

Ah great thanks. We are on 19.1.x at the moment - is this a later feature?

[Giovanni]

Yes, H7 support has been enhanced, you may look at current code and do this at application level before calling halInit().

Giovanni

[andypiper]

Yes, H7 support has been enhanced, you may look at current code and do this at application level before calling halInit().

Giovanni

Thanks, which LLD? I was looking for MPU but that doesn't exist?

[Giovanni]

It is not an LLD, it is under /os/hal/ports/common/ARMCMx.

Giovanni

[andypiper]

It is not an LLD, it is under /os/hal/ports/common/ARMCMx.

Giovanni

Thanks!

[andypiper]

Hi,

No need to struggle too much, in mcuconf.h there is this:

Code: Select all

/*
 * Memory attributes settings.
 */
#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
#define STM32_NOCACHE_SRAM3                 TRUE


The related code is in hal_lld.c, you can use that as example.

Giovanni

Ah great thanks. We are on 19.1.x at the moment - is this a later feature?

It looks like I can just set STM32_NOCACHE_SRAM1_SRAM2 and use memory from 0x30000000 for now?

[Giovanni]

You can make any combination of the two settings, you could also add extra regions if you want.

Giovanni

[andypiper]

You can make any combination of the two settings, you could also add extra regions if you want.

Giovanni

Thanks Giovanni. So I think this will clear up any DMA problems I am currently having (I notice on F7 we are using DTCM memory so that may explain some of the differences I am seeing between F7 and H7).

Is the gcc volatile keyword observed correctly for data located in cachable memory?

[Giovanni]

On F7 DTCM is accessible by DMAs, this is not the case on the H7. F7 is generally much easier to use.

Is the gcc volatile keyword observed correctly for data located in cachable memory?

No, the compiler is not cache-aware.

Giovanni

[andypiper]

On F7 DTCM is accessible by DMAs, this is not the case on the H7. F7 is generally much easier to use.

Is the gcc volatile keyword observed correctly for data located in cachable memory?

No, the compiler is not cache-aware.

Giovanni

Urg, so I guess the next question is do the ChibiOS mutexs provide a memory barrier (I guess not since you need help frome the compiler) and does it matter on a single core H743? If I have multiple threads interacting through SRAM what do I need to do to ensure I don't get dirty reads and the like.