I have a system which uses the SDMMC driver with a STM32H743, and I'm bumping into a weird issue.
sdcConnect() fails in sdc_detect_bus_clk(). If I simply add a return early and force to run at 25 MHz, everything seems to work fine:
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@@ -323,6 +323,7 @@ static bool sdc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) {
/* Safe default.*/
*clk = SDC_CLK_25MHz;
+ return HAL_SUCCESS; // TEMP^M
/* Looks like only "high capacity" cards produce meaningful results during
this clock detection procedure.*/
but the method as is fails in sdc_lld_read_special(). The exact place where it fails is in sdc_lld_wait_transaction_end(),
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if ((sdcp->sdmmc->STA & SDMMC_STA_DATAEND) == 0) {
osalSysUnlock();
return HAL_FAILED;
}
but really all that happens is that the transaction fails so that function gets woken up by the interrupt to process the completion (or error in this case). I can't figure out why the error happens or a workaround other than forcing to 25 MHz, but the registers indicate that it's an RX fifo overrun/IDMA transfer error. STA is 0x8001020.
Also, it seems that the default for STM32_SDMMC_MAXCLK is set to 50MHz, but it could be upped substantially for the H7. From Table 59/page 352 of the manual it seems that 100 MHz is safe for all voltage scaling settings, and can go up to 250. I have tested below 50 MHz, but also tried to increase to almost 100 to see if it changed anything, unsuccessfully.
GB
