STM32G030 support.

ChibiOS public support forum for topics related to the STMicroelectronics STM32 family of micro-controllers.

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rew
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STM32G030 support.

Postby rew » Wed Aug 18, 2021 5:25 pm

Hi,

Has anybody gotten chibios to run on the STM32G030 ?
I (perhaps unfounded) expected it top be quite similar to the F030, expecting it to even be binary compatible.

Well... that didn't happen. It's got lots of important differences. But now that I've configured board.h to use the proper CPU, I'm in need of a reasonable start for an mcuconf.h file. I started modifying the F030 version, but after 15 minutes I've moved on like 3 lines. No end in sight.

Suggestions?

Anybody got a sample project on G030?

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Re: STM32G030 support.

Postby Giovanni » Wed Aug 18, 2021 6:28 pm

It would be close to other G0s not F0s for sure.

I have not worked with that device yet.

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Re: STM32G030 support.

Postby rew » Thu Aug 19, 2021 3:28 pm

It seems that this CPU doesn't have TIM2.

I've disabled (left alone from the demo app) GPT/ICU/PWM on that timer. Why is it still erroring out with TIM2 problems?

Code: Select all

In file included from ../../../os/hal/include/hal_st.h:30,
                 from ../../../os/hal/include/hal.h:296,
                 from ../../../os/hal/src/hal.c:25:
../../../os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h:157:45: warning: "STM32_TIM2_CHANNELS" is not defined, evaluates to 0 [-Wundef]
  157 | #define ST_LLD_NUM_ALARMS                   STM32_TIM2_CHANNELS
      |                                             ^~~~~~~~~~~~~~~~~~~
../../../os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.h:613:33: note: in expansion of macro 'ST_LLD_NUM_ALARMS'
  613 |     (STM32_ST_OVERRIDE_ALARMS > ST_LLD_NUM_ALARMS)


Edit:

I've added a section to the stm32_registry that includes;

Code: Select all

#define STM32_HAS_TIM2                      FALSE^M


Edit2: Ah... I was searching for a config indicating "TIM2". I was searching for SYSTICK or SYST....
CH_ST_USE_TIMER 2

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Re: STM32G030 support.

Postby rew » Fri Aug 20, 2021 2:37 pm

OK.

I have the impression that my code (and chibios) now runs on the target CPU. However calls to "PalSetPadMode" don't seem to have any effect.

I am now directly writing a value into the GPIOA->MODER and... nothing.
I am now useing the debuger to directly write into the GPIOA->MODER but still nothing.

The value starts out as ebffffff and I can't change it to anything else. What am I missing? Is there some sort of "protected mode" that prevents me from writing into those registers? A lock bit? (write this to one before you can change the GPIO configuration) ? (the eb means PA14 and 13 are AF, swdio and swdck in this case. )

Update: Chibios fails to enable the GPIOS in the RCC. Doing this manually I now have a blinking led.
Last edited by rew on Fri Aug 20, 2021 3:11 pm, edited 1 time in total.

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Re: STM32G030 support.

Postby Giovanni » Fri Aug 20, 2021 2:55 pm

Verify GPIO clocks.

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Re: STM32G030 support.

Postby rew » Mon Aug 23, 2021 4:51 pm

On STM32F030 the Io ports are enabled in the AHBENR, the STM32G030 has a separate registers IOPENR.

I copied the STM32G071 nucleo example code, but this is also wrong in its board file: ./os/hal/boards/ST_NUCLEO64_G071RB/board.c I checked, it doesn't have the flags in the AHB_ENR and it has the separate IOPENR like my '030.

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Re: STM32G030 support.

Postby rew » Thu Sep 02, 2021 5:47 pm

I now have a basic application running on my development board. I have offered you before: if you want one of my development board, I can send it to you for free. (If you don't want to be sponsored, I'll have to think up a reasonable price and make it available for everybody. That's fine too.) Just let me know what you want.

I'll make a diff later, there was a small change necessary besides adding things to the registry: The DMA driver until now) didn't handle an M0 with 5 and not 7 DMA channels.

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Re: STM32G030 support.

Postby Giovanni » Thu Sep 02, 2021 5:59 pm

Hi,

No need to send boards, as soon there is some Nucleo available I can get it for free from ST.

Just post your changes so I can start looking at what is needed.

Giovanni

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Re: STM32G030 support.

Postby rew » Fri Sep 03, 2021 3:16 pm

I think that this is the nucleo that ST thinks should cover the 'G030 as well.

https://www.st.com/content/st_com/en/pr ... 031k8.html

I have posted my current diff here: https://prive.bitwizard.nl/G030_support.diff

I copied one of the demos and edited it to work. The board.h and .c need to be moved where they belong when they go in the tree.


as you can see I edited the board files to make all pins input by default. I'd very much like chibios to supply such a board file for each supported processor. (or even ONLY supply that, and have the demo and testhal programs demonstrate the use of PalSetLineMode () and family)

Code like the GPIO port setup seems to be duplicated in dozens of board.c files. IMHO should be moved to inside "chibios".

You say you generate the board.h files with a tool. I've never gotten that tool to work on my system.

The patch in dma1_ch4567 is obvious ('G030 has 45, not 67).

The patch of stm32_pll_v2.inc was an ugly attempt to get that Q_MAX value defined. IIRC that didn't work there, but in any case it doesn't belong there. You'll know where to put it.

The patch of hal_lld.c : the G030 doesn't have the ACR DBG_SWEN bit. Again should be added somwhere better, not here.

hal_lld.h : Somehow I could't get it to recognize the define I made for my processor.

G0xx/stm32_registry.h I copied over the 070 and changed what I ran into.... So I did encounte the "DMA1_NUM_CHANNELS" that is different, but no guarantees that there aren't other changes required.

For the timers: I see the reference manual describing 9 timers, but the datasheet summarizes that there are only 5 timers. A quick lookaround in the manuals/datasheet: I couldn't find where to look to find which ones are not available.

Similarly I think that more uarts look enable than what it really has. Ah! for UART there is a nice table on page 777 of the reference manual. OK. I think I've fixed that: disabled uart 3-4-5.

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Re: STM32G030 support.

Postby alexblack » Tue Sep 21, 2021 7:51 am

Hi.
I have some trouble with ADC in STM32G030 mcu. I wanted to get ADC data at regular intervals and used the timer 3 for that. I used this methode to produce ADC data in another MCUs many times and all works well, but in this MCU the program continously loop in DMA IRQ handler. It seems that the IRQ flags do not want to clear. I also tried do it under the debuger by hand and it not cleared. I also disable the TIM under the debugger and the IRQ flag stay in active state and not cleared by hand too. Also I used SPI driver and it works well with DMA. What it can be?
ADC worked because converted data appears in the buffer. If I REM the code for timer - there is no data from ADC and program do not run to DMA handler.
I used ChbiOS 21.6.x stable branch (. This is my code for configuration the ADC and TIM:

Code: Select all

// Activates the ADC1 driver and the thermal sensor.
  adcStart(&ADCD1, NULL);
 
  /* ADC conversion group. */
  static const ADCConversionGroup adcgrpcfg = {
    //circular
    true,
    //num_channels
    ADC_NUM_CHANNELS, // 7
    // end_cb
    adccallback,
    // error_cb
    adcerrorcallback,
    //cfgr1
    0
    | ADC_CFGR1_CONT
    | ADC_CFGR1_RES_12BIT
    | ADC_CFGR1_EXTEN_RISING
    | ADC_CFGR1_EXTSEL_SRC(3),
    // cfgr2
    0,
    // tr1
    ADC_TR_DISABLED,
    // tr2
    ADC_TR_DISABLED,
    // tr3
    ADC_TR_DISABLED,
    // awd2cr
    0U,
    // awd3cr
    0U,
    // smpr
    ADC_SMPR_SMP_39P5,
    // chselr
    0
    | ADC_CHSELR_CHSEL2
    | ADC_CHSELR_CHSEL3
    | ADC_CHSELR_CHSEL4
    | ADC_CHSELR_CHSEL5
    | ADC_CHSELR_CHSEL6
    | ADC_CHSELR_CHSEL7
    | ADC_CHSELR_CHSEL8
  };
 
  // Starts an ADC conversion.
  adcStartConversion(&ADCD1, &adcgrpcfg, ADC_SAMPLES, 1);
 
  // Configure TIM3 to generathe the TRGO signal for starting the ADC
  static const GPTConfig TMRconf = {
    // frequency
    1000000,
    // callback
    NULL,
    // cr2
    // 010: Update- The update event is selected as trigger output (TRGO).
    TIM_CR2_MMS_1,
    // dier
    0
  };
  gptStart(&ADC_TMR_DRIVER, &TMRconf);
  chSysLock(); 
  gptStartContinuousI(&ADC_TMR_DRIVER, ADC_SPEED);
  // disable useless IRQ from TIM
  ADC_TMR_DRIVER.tim->DIER = 0;
  chSysUnlock();

Mcu config files is:

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

/*
 * STM32G0xx drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 3...0        Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#ifndef MCUCONF_H
#define MCUCONF_H

#define STM32G0xx_MCUCONF
#define STM32G030_MCUCONF
#define STM32G070_MCUCONF
//#define STM32G081_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_CLOCK_DYNAMIC                 TRUE
#define STM32_VOS                           STM32_VOS_RANGE1
#define STM32_PWR_CR2                       (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
#define STM32_PWR_CR3                       (PWR_CR3_EIWUL)
#define STM32_PWR_CR4                       (0U)
#define STM32_PWR_PUCRA                     (0U)
#define STM32_PWR_PDCRA                     (0U)
#define STM32_PWR_PUCRB                     (0U)
#define STM32_PWR_PDCRB                     (0U)
#define STM32_PWR_PUCRC                     (0U)
#define STM32_PWR_PDCRC                     (0U)
#define STM32_PWR_PUCRD                     (0U)
#define STM32_PWR_PDCRD                     (0U)
#define STM32_PWR_PUCRF                     (0U)
#define STM32_PWR_PDCRF                     (0U)
#define STM32_HSIDIV_VALUE                  1
#define STM32_HSI16_ENABLED                 TRUE
#define STM32_HSE_ENABLED                   FALSE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_LSE_ENABLED                   FALSE
#define STM32_SW                            STM32_SW_PLLRCLK
#define STM32_PLLSRC                        STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE                    2
#define STM32_PLLN_VALUE                    8
#define STM32_PLLP_VALUE                    2
#define STM32_PLLR_VALUE                    2
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE                          STM32_PPRE_DIV1
#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE                        STM32_MCOPRE_DIV1
#define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK

/*
 * Peripherals clocks and sources.
 */
#define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
#define STM32_CECSEL                        STM32_CECSEL_HSI16DIV
#define STM32_I2C1SEL                       STM32_I2C1SEL_PCLK
#define STM32_I2S1SEL                       STM32_I2S1SEL_SYSCLK
#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK
#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK
//#define STM32_TIM1SEL                       STM32_TIM1SEL_TIMPCLK
//#define STM32_TIM15SEL                      STM32_TIM15SEL_TIMPCLK
//#define STM32_RNGSEL                        STM32_RNGSEL_HSI16
#define STM32_RNGDIV_VALUE                  1
#define STM32_ADCSEL                        STM32_ADCSEL_PLLPCLK
#define STM32_RTCSEL                        STM32_RTCSEL_NOCLOCK

/*
 * Shared IRQ settings.
 */
#define STM32_IRQ_EXTI0_1_PRIORITY          3
#define STM32_IRQ_EXTI2_3_PRIORITY          3
#define STM32_IRQ_EXTI4_15_PRIORITY         3
#define STM32_IRQ_EXTI1921_PRIORITY         3

#define STM32_IRQ_USART1_PRIORITY           2
#define STM32_IRQ_USART2_PRIORITY           2
#define STM32_IRQ_USART3_4_LP1_PRIORITY     2

#define STM32_IRQ_TIM1_UP_PRIORITY          1
#define STM32_IRQ_TIM1_CC_PRIORITY          1
#define STM32_IRQ_TIM2_PRIORITY             1
#define STM32_IRQ_TIM3_PRIORITY             1
#define STM32_IRQ_TIM6_PRIORITY             1
#define STM32_IRQ_TIM7_PRIORITY             1
#define STM32_IRQ_TIM14_PRIORITY            1
#define STM32_IRQ_TIM15_PRIORITY            1
#define STM32_IRQ_TIM16_PRIORITY            1
#define STM32_IRQ_TIM17_PRIORITY            1

/*
 * ADC driver system settings.
 */
#define STM32_ADC_USE_ADC1                  TRUE
#define STM32_ADC_ADC1_CKMODE               STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE           2

/*
 * DAC driver system settings.
 */
#define STM32_DAC_DUAL_MODE                 FALSE
#define STM32_DAC_USE_DAC1_CH1              FALSE
#define STM32_DAC_USE_DAC1_CH2              FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     3
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     3
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM1                  FALSE
#define STM32_GPT_USE_TIM3                  TRUE
#define STM32_GPT_USE_TIM14                 FALSE
#define STM32_GPT_USE_TIM16                 FALSE
#define STM32_GPT_USE_TIM17                 FALSE

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_BUSY_TIMEOUT              50
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY         3
#define STM32_I2C_I2C2_IRQ_PRIORITY         3
#define STM32_I2C_I2C1_DMA_PRIORITY         3
#define STM32_I2C_I2C2_DMA_PRIORITY         3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM1                  FALSE
#define STM32_ICU_USE_TIM3                  FALSE
#define STM32_ICU_USE_TIM14                 FALSE
#define STM32_ICU_USE_TIM16                 FALSE
#define STM32_ICU_USE_TIM17                 FALSE

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_TIM1                  TRUE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM14                 FALSE
#define STM32_PWM_USE_TIM16                 FALSE
#define STM32_PWM_USE_TIM17                 TRUE

/*
 * RTC driver system settings.
 */
#define STM32_RTC_PRESA_VALUE               32
#define STM32_RTC_PRESS_VALUE               1024
#define STM32_RTC_CR_INIT                   0
#define STM32_RTC_TAMPCR_INIT               0

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             FALSE

/*
 * SIO driver system settings.
 */
#define STM32_SIO_USE_USART1                FALSE
#define STM32_SIO_USE_USART2                FALSE

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  FALSE
#define STM32_SPI_USE_SPI2                  TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         2
#define STM32_SPI_SPI2_IRQ_PRIORITY         2
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY               2
#define STM32_ST_USE_TIMER                  14

/*
 * TRNG driver system settings.
 * NOTE: STM32G081 only.
 */
#define STM32_TRNG_USE_RNG1                 FALSE

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART3               FALSE
#define STM32_UART_USE_UART4                FALSE
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART3_DMA_PRIORITY      0
#define STM32_UART_UART4_DMA_PRIORITY       0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

/*
 * WDG driver system settings.
 */
#define STM32_WDG_USE_IWDG                  TRUE

#endif /* MCUCONF_H */



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