All good Ilya.
Nice that the WB55 has 8 endpoints (can get 3 VCOMs if you need them in an application).
--
Bob
STM32WB55 support
- Giovanni
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Re: STM32WB55 support
Hi bob,
I renamed that file, maybe you have a problem in your local copy, try to delete the directory and update again should it happen again.
Giovanni
I renamed that file, maybe you have a problem in your local copy, try to delete the directory and update again should it happen again.
Giovanni
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Re: STM32WB55 support
Hi Giovanni and Bob,
Thank you for accepting previous patches. I've attached more patches in the tarball with changes related to the clock tree and CMSIS updates, ready for review.
Commit summary:
PS: I still struggle with the USB_CDC test. I use USBv1 because STM32WB doesn't support OTG. The problem I'm debugging right now is related to that setting STM32_USB->CNTR to cntr is ignored, i.e. STM32_USB->CNTR is 0 even when cntr has a correct value. This happens in usb_lld_reset() invoked by usb_lld_start() at the end. I've updated the clock configuration for the test (not included in the tarball) and I plan to make a couple of more debug rounds, will update you.
Best regards,
Ilya.
Thank you for accepting previous patches. I've attached more patches in the tarball with changes related to the clock tree and CMSIS updates, ready for review.
Commit summary:
Code: Select all
* STM32WB: update clock tree configuration
* Update HSE configuration
* HSE bypass is not supported
* Removed STM32_HSE_BYPASS, STM32_HSECLK_BYP_MIN and STM32_HSECLK_BYP_MAX
* Updated board template and config files
* Limit HSE to only 32Mhz (set both STM32_HSECLK_MAX and
STM32_HSECLK_MIN to 32000000)
* Add extended clock recovery register configuration (RCC->EXTCFGR)
* Add STM32_C2HPRE with dividers 1,2,...,512 (for CPU2 and HCLK2)
* Add STM32_SHDHPRE with deviders 1,2,...,512 (for HCLK4, AHB4, Flash memory SRAM2)
* Add STM32_RFCSSSEL with HSI16 and HSE/2 sources (for HCLK5, APB3, AHB5, Radio system)
* Add 3, 5, 6, 10 and 32 dividers for HPRE
* Update the default value of STM32_HSI16_ENABLED to True because used
by STM32_RFCSSSEL
* Update STM32_*_MIN/MAX values used for both VOS ranges according to
datasheet and reference manual
* Remove FLASH_ACR_LATENCY_4WS as not supported
* STM32WB: update CMSIS files to v1.10.0
* In addition included STM32WB30XX, STM32WB35XX and STM32WB5MXX
PS: I still struggle with the USB_CDC test. I use USBv1 because STM32WB doesn't support OTG. The problem I'm debugging right now is related to that setting STM32_USB->CNTR to cntr is ignored, i.e. STM32_USB->CNTR is 0 even when cntr has a correct value. This happens in usb_lld_reset() invoked by usb_lld_start() at the end. I've updated the clock configuration for the test (not included in the tarball) and I plan to make a couple of more debug rounds, will update you.
Best regards,
Ilya.
- Attachments
-
- STM32WBxx-424d6e.zip
- STM32WBXX clock tree and CMSIS updates
- (361.86 KiB) Downloaded 153 times
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Re: STM32WB55 support
Giovanni,
Thank you for answering. Yes, the clock is fine. I think that I found the problem. USBv1 uses its own structure, stm32_usb_t, and uses USB_BASE as its address or (APB1PERIPH_BASE + 0x5C00) if USB_BASE is not defined. However, STM32WB has different offsets (stm32wb55xx.h):
I'm going to change USBv1 to account this specific of STM32WB. However, I wonder what was the reason to use custom stm32_usb_t structure instead of USB_TypeDef and proper definitions provided by CMSIS? Does it make sense to change USBv1 to use CMSIS instead? I see lots of other hardcoded values.
Best regards,
Ilya.
Thank you for answering. Yes, the clock is fine. I think that I found the problem. USBv1 uses its own structure, stm32_usb_t, and uses USB_BASE as its address or (APB1PERIPH_BASE + 0x5C00) if USB_BASE is not defined. However, STM32WB has different offsets (stm32wb55xx.h):
Code: Select all
#define USB1_BASE (APB1PERIPH_BASE + 0x00006800UL)
#define USB1_PMAADDR (APB1PERIPH_BASE + 0x00006C00UL)
I'm going to change USBv1 to account this specific of STM32WB. However, I wonder what was the reason to use custom stm32_usb_t structure instead of USB_TypeDef and proper definitions provided by CMSIS? Does it make sense to change USBv1 to use CMSIS instead? I see lots of other hardcoded values.
Best regards,
Ilya.
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Re: STM32WB55 support
Hi,
This driver is ancient, there were problems with headers back then. It would be possible to change it to use CMSIS headers now but then it should be re-tested on all platforms. It is possible that we would hit differences in headers too, those headers are not very consistent.
It is not the only driver using a custom structure anyway, see also OTG, TIM, GPIO.
Giovanni
This driver is ancient, there were problems with headers back then. It would be possible to change it to use CMSIS headers now but then it should be re-tested on all platforms. It is possible that we would hit differences in headers too, those headers are not very consistent.
It is not the only driver using a custom structure anyway, see also OTG, TIM, GPIO.
Giovanni
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Re: STM32WB55 support
Giovanni,
Thank you for accepting these patches. I noticed that new files, such as stm32wb30xx.h, stm32wb35xx.h and stm32wb5mxx.h, hadn't been added.
Best regards,
Ilya.
Thank you for accepting these patches. I noticed that new files, such as stm32wb30xx.h, stm32wb35xx.h and stm32wb5mxx.h, hadn't been added.
Best regards,
Ilya.
- Giovanni
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Re: STM32WB55 support
Giovanni,
Thank you for adding those files. I've attached a tarball with patches for USBv1 to account STM32WB specifics and clock configuration updates for testhal multi USB_CDC. These patches are ready for review.
Summary of commit messages:
Best regards,
Ilya.
Thank you for adding those files. I've attached a tarball with patches for USBv1 to account STM32WB specifics and clock configuration updates for testhal multi USB_CDC. These patches are ready for review.
Summary of commit messages:
Code: Select all
* STM32WB: update clock configuration for multi USB_CDC
* STM32WB: use specific USB and USB RAM base addresses in USBv1
There are multiple MCUs in the WB family that support USB 2.0 FS:
STM32WB55xx, STM32WB35xx and stm32WB5mxx. Their CMSIS headers
have more specific USB and USB RAM registers base addresses, namely:
#define USB1_BASE (APB1PERIPH_BASE + 0x00006800UL)
#define USB1_PMAADDR (APB1PERIPH_BASE + 0x00006C00UL)
And they differ from USB_BASE and USB_PMAADDR addresses used by USBv1
(can be found in stm32wb55xx.h):
#define USB_BASE (0x40005C00UL)
#define USB_PMAADDR_Pos (13U)
#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos)
#define USB_PMAADDR USB_PMAADDR_Msk // 0x40006000UL
USBv1 is changed to use USB1_BASE and USB1_PMAADDR if they are defined
to account STM32WB specific addresses.
Best regards,
Ilya.
- Attachments
-
- STM32WBxx-b4186f.zip
- STM32WB USBv1 and USB_CDC
- (2.72 KiB) Downloaded 163 times
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