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Re: [DEV] RP2040 support
Posted: Thu Aug 26, 2021 2:33 pm
by hanya
Thank you for your response. I will try to choose collect mode for set address.
And I found the following description about the SET_ADDRESS request in the pico-sdk.
Code: Select all
From pico-sdk, dev_lowlevel.c
/**
* @brief Handles a SET_ADDR request from the host. The actual setting of the device address in
* hardware is done in ep0_in_handler. This is because we have to acknowledge the request first
* as a device with address zero.
*
* @param pkt, the setup packet from the host.
*/
void usb_set_device_address(volatile struct usb_setup_packet *pkt) {
It looks I could choose set of USB_SET_ADDRESS_ACK_SW and USB_LATE_SET_ADDRESS.
But I have trouble on the IN transfer after the SET_ADDRESS request. It would not finished, so set_address callback would not called.
Re: [DEV] RP2040 support
Posted: Thu Aug 26, 2021 3:26 pm
by xyz
hanya wrote:Thank you for your response. I will try to choose collect mode for set address.
And I found the following description about the SET_ADDRESS request in the pico-sdk.
Code: Select all
From pico-sdk, dev_lowlevel.c
/**
* @brief Handles a SET_ADDR request from the host. The actual setting of the device address in
* hardware is done in ep0_in_handler. This is because we have to acknowledge the request first
* as a device with address zero.
*
* @param pkt, the setup packet from the host.
*/
void usb_set_device_address(volatile struct usb_setup_packet *pkt) {
It looks I could choose set of USB_SET_ADDRESS_ACK_SW and USB_LATE_SET_ADDRESS.
But I have trouble on the IN transfer after the SET_ADDRESS request. It would not finished, so set_address callback would not called.
Hi hanya, I've sent you a PR on github which fixes this and some other issues, please check it at
https://github.com/hanya/ChibiOS-Contrib/pull/1
Re: [DEV] RP2040 support
Posted: Fri Aug 27, 2021 4:06 am
by xyz
There's also a bug in chibios gpio implementation in os/hal/ports/RP/LLD/GPIOv1/hal_pal_lld.h
Code: Select all
diff --git a/os/hal/ports/RP/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/RP/LLD/GPIOv1/hal_pal_lld.h
index 34b88855d..dae4079f7 100644
--- a/os/hal/ports/RP/LLD/GPIOv1/hal_pal_lld.h
+++ b/os/hal/ports/RP/LLD/GPIOv1/hal_pal_lld.h
@@ -389,7 +389,7 @@ __STATIC_INLINE void __pal_lld_pad_set_mode(ioportid_t port,
ctrlbits = (mode & 0x007FFFFFU) >> 0U;
oebits = (mode & 0x00800000U) >> 23U;
- padbits = (mode & 0xF0000000U) >> 24U;
+ padbits = (mode & 0xFF000000U) >> 24U;
/* Setting up GPIO direction first.*/
if (oebits != 0U) {
Currently it does "mode & 0xF0000000U" which ends up ignoring low 4 of gpio config bits, e.g. PAL_RP_PAD_PUE, so pull-up never ends up enabled.
Re: [DEV] RP2040 support
Posted: Fri Aug 27, 2021 8:37 am
by FXCoder
Fixed in trunk.
Re: [DEV] RP2040 support
Posted: Fri Aug 27, 2021 11:49 am
by hanya
I have updated code a bit. Now USB state can be reached to configured state.
The lsusb command shows correct information about its descriptors.
HID test code seems working but there are some data error shown, maybe PID problem.
The shell through CDC does not start yet.
Re: [DEV] RP2040 support
Posted: Sun Aug 29, 2021 2:58 am
by hanya
Hi xyz, thanks for your PR. I have fixed some of them before I notice your PR. But I did not noticed about wrong setting of buffer offset.
I added shell example. After few fix, ChibiOS/RT Shell is working well now.
Re: [DEV] RP2040 support
Posted: Wed Sep 01, 2021 1:01 pm
by findeluxe
Hi, thanks for this port, it looks very promising. I've noticed that os/hal/ports/RP/LLD/TIMERv1/driver.mk already refers to hal_gpt_lld.c (for GPT support), but it seems that this is either not implemented yet - or maybe you forgot to commit those files?
I tried to use the pico-sdk library for GPT-like functionality (same as I did for I2C, which more or less works), but frankly, it's a giant mess trying to mix DMA/IRQ usage from both ChibiOS and pico-sdk...
Re: [DEV] RP2040 support
Posted: Wed Sep 01, 2021 1:56 pm
by Giovanni
Hi,
GPT is in preparation so not finished.
In general Pico-SDK is written like it is the only SW in the system, it does not play well with 3rd parties libraries, lots of name conflicts and assumptions in there. I hoped to "use" it but I right now I am just looking at it as reference code.
Clock initialization is an exception, we are using it as-is, eventually we will remove the dependency on that too.
Any idea about how to submit feedback? they could be interested in the integration problems we are facing.
Giovanni
Re: [DEV] RP2040 support
Posted: Wed Sep 01, 2021 8:44 pm
by steved
Giovanni wrote:Any idea about how to submit feedback? they could be interested in the integration problems we are facing.
Submit an "issue" at
https://github.com/raspberrypi/pico-sdk is your best bet.
Suggest you are cautious - in the beginning the RPT got some fairly fierce criticism, mostly from experienced software developers, about some of their implementation choices. (What they have done is great for raw beginners, and the chip datasheets put many larger companies to shame; but I'm not sure they really considered third parties adding the RP2040 to other platforms).
If you want to provoke a more public reaction (most users don't look at Github, as far as I can see), another forum post at
https://www.raspberrypi.org/forums/viewforum.php?f=145.
Incidentally, they are working on a FreeRTOS port, which may also give some hints:
https://github.com/PicoCPP/RPI-pico-FreeRTOShttps://github.com/kilograham/FreeRTOS- ... GCC/RP2040https://github.com/kilograham/FreeRTOS- ... GCC/RP2040https://github.com/kilograham/FreeRTOS/ ... %2B_RP2040Don't think its complete yet.
Re: [DEV] RP2040 support
Posted: Wed Sep 15, 2021 1:41 am
by hanya
Please add structure definition for PWM register.
Code: Select all
diff --git a/os/common/ext/RP/RP2040/rp2040.h b/os/common/ext/RP/RP2040/rp2040.h
index 01c911d..7423d88 100644
--- a/os/common/ext/RP/RP2040/rp2040.h
+++ b/os/common/ext/RP/RP2040/rp2040.h
@@ -896,6 +896,67 @@ struct {
} CLR;
} ADC_TypeDef;
+typedef struct {
+ struct {
+ __IO uint32_t CSR;
+ __IO uint32_t DIV;
+ __IO uint32_t CTR;
+ __IO uint32_t CC;
+ __IO uint32_t TOP;
+ } CH[8];
+ __IO uint32_t EN;
+ __IO uint32_t INTR;
+ __IO uint32_t INTE;
+ __IO uint32_t INTF;
+ __I uint32_t INTS;
+ __I uint32_t resvdpwm[979];
+ struct {
+ struct {
+ __IO uint32_t CSR;
+ __IO uint32_t DIV;
+ __IO uint32_t CTR;
+ __IO uint32_t CC;
+ __IO uint32_t TOP;
+ } CH[8];
+ __IO uint32_t EN;
+ __IO uint32_t INTR;
+ __IO uint32_t INTE;
+ __IO uint32_t INTF;
+ __I uint32_t INTS;
+ __I uint32_t resvdpwm[979];
+ } XOR;
+ struct {
+ struct {
+ __IO uint32_t CSR;
+ __IO uint32_t DIV;
+ __IO uint32_t CTR;
+ __IO uint32_t CC;
+ __IO uint32_t TOP;
+ } CH[8];
+ __IO uint32_t EN;
+ __IO uint32_t INTR;
+ __IO uint32_t INTE;
+ __IO uint32_t INTF;
+ __I uint32_t INTS;
+ __I uint32_t resvdpwm[979];
+ } SET;
+ struct {
+ struct {
+ __IO uint32_t CSR;
+ __IO uint32_t DIV;
+ __IO uint32_t CTR;
+ __IO uint32_t CC;
+ __IO uint32_t TOP;
+ } CH[8];
+ __IO uint32_t EN;
+ __IO uint32_t INTR;
+ __IO uint32_t INTE;
+ __IO uint32_t INTF;
+ __I uint32_t INTS;
+ __I uint32_t resvdpwm[979];
+ } CLR;
+} PWM_TypeDef;
+
typedef struct {
__IO uint32_t DEVADDRCTRL;
__IO uint32_t INTEPADDRCTRL[15]; /* USB_HOST_INTERRUPT_ENDPOINTS */
@@ -2476,6 +2537,190 @@ typedef struct {
#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_Msk (3U << I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_Pos)
#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_Msk
/** @} */
+
+/**
+ * @name PWM bits definitions
+ * @{
+ */
+#define PWM_CSR_PH_ADV_Pos 7U
+#define PWM_CSR_PH_ADV_Msk (1U << PWM_CSR_PH_ADV_Pos)
+#define PWM_CSR_PH_ADV PWM_CSR_PH_ADV_Msk
+#define PWM_CSR_PH_RET_Pos 6U
+#define PWM_CSR_PH_RET_Msk (1U << PWM_CSR_PH_RET_Pos)
+#define PWM_CSR_PH_RET PWM_CSR_PH_RET_Msk
+#define PWM_CSR_DIVMODE_Pos 4U
+#define PWM_CSR_DIVMODE_Msk (0x3U << PWM_CSR_DIVMODE_Pos)
+#define PWM_CSR_DIVMODE(n) ((n) << PWM_CSR_DIVMODE_Pos)
+#define PWM_CSR_B_INV_Pos 3U
+#define PWM_CSR_B_INV_Msk (1U << PWM_CSR_B_INV_Pos)
+#define PWM_CSR_B_INV PWM_CSR_B_INV_Msk
+#define PWM_CSR_A_INV_Pos 2U
+#define PWM_CSR_A_INV_Msk (1U << PWM_CSR_A_INV_Pos)
+#define PWM_CSR_A_INV PWM_CSR_A_INV_Msk
+#define PWM_CSR_PH_CORRECT_Pos 1U
+#define PWM_CSR_PH_CORRECT_Msk (1U << PWM_CSR_PH_CORRECT_Pos)
+#define PWM_CSR_PH_CORRECT PWM_CSR_PH_CORRECT_Msk
+#define PWM_CSR_EN_Pos 0U
+#define PWM_CSR_EN_Msk (1U << PWM_CSR_EN_Pos)
+#define PWM_CSR_EN PWM_CSR_EN_Msk
+#define PWM_CSR_PH_CORRECT_PHASE_CORRECT_MODULATION (1U << PWM_CSR_PH_CORRECT_Pos)
+#define PWM_CSR_PH_CORRECT_TRAILING_EDGE (0U << PWM_CSR_PH_CORRECT_Pos)
+#define PWM_CSR_DIVMODE_FREE PWM_CSR_DIVMODE(0U)
+#define PWM_CSR_DIVMODE_GATED PWM_CSR_DIVMODE(1U)
+#define PWM_CSR_DIVMODE_RISING_EDGE PWM_CSR_DIVMODE(2U)
+#define PWM_CSR_DIVMODE_FALING_EDGE PWM_CSR_DIVMODE(3U)
+
+#define PWM_DIV_INT_Pos 4U
+#define PWM_DIV_INT_Msk (0xFFU << PWM_DIV_INT_Pos)
+#define PWM_DIV_INT PWM_DIV_INT_Msk
+#define PWM_DIV_FRAC_Pos 0U
+#define PWM_DIV_FRAC_Msk (0xFU << PWM_DIV_FRAC_Pos)
+#define PWM_DIV_FRAC PWM_DIV_FRAC_Msk
+
+#define PWM_CTR_COUNTER_Pos 0U
+#define PWM_CTR_COUNTER_Msk (0xFFFFU << PWM_CTR_COUNTER_Pos)
+#define PWM_CTR_COUNTER PWM_CTR_COUNTER_Msk
+
+#define PWM_CC_B_Pos 16U
+#define PWM_CC_B_Msk (0xFFFFU << PWM_CC_B_Pos)
+#define PWM_CC_B PWM_CC_B_Msk
+#define PWM_CC_A_Pos 0U
+#define PWM_CC_A_Msk (0xFFFFU << PWM_CC_A_Pos)
+#define PWM_CC_A PWM_CC_A_Msk
+
+#define PWM_TOP_VALUE_Pos 0U
+#define PWM_TOP_VALUE_Msk (0xFFFFU << PWM_TOP_VALUE_Pos)
+#define PWM_TOP_VALUE PWM_TOP_VALUE_Msk
+
+#define PWM_EN_CH7_Pos 7U
+#define PWM_EN_CH7_Msk (1U << PWM_EN_CH7_Pos)
+#define PWM_EN_CH7 PWM_EN_CH7_Msk
+#define PWM_EN_CH6_Pos 6U
+#define PWM_EN_CH6_Msk (1U << PWM_EN_CH6_Pos)
+#define PWM_EN_CH6 PWM_EN_CH6_Msk
+#define PWM_EN_CH5_Pos 5U
+#define PWM_EN_CH5_Msk (1U << PWM_EN_CH5_Pos)
+#define PWM_EN_CH5 PWM_EN_CH5_Msk
+#define PWM_EN_CH4_Pos 4U
+#define PWM_EN_CH4_Msk (1U << PWM_EN_CH4_Pos)
+#define PWM_EN_CH4 PWM_EN_CH4_Msk
+#define PWM_EN_CH3_Pos 3U
+#define PWM_EN_CH3_Msk (1U << PWM_EN_CH3_Pos)
+#define PWM_EN_CH3 PWM_EN_CH3_Msk
+#define PWM_EN_CH2_Pos 2U
+#define PWM_EN_CH2_Msk (1U << PWM_EN_CH2_Pos)
+#define PWM_EN_CH2 PWM_EN_CH2_Msk
+#define PWM_EN_CH1_Pos 1U
+#define PWM_EN_CH1_Msk (1U << PWM_EN_CH1_Pos)
+#define PWM_EN_CH1 PWM_EN_CH1_Msk
+#define PWM_EN_CH0_Pos 0U
+#define PWM_EN_CH0_Msk (1U << PWM_EN_CH0_Pos)
+#define PWM_EN_CH0 PWM_EN_CH0_Msk
+
+#define PWM_INTR_CH7_Pos 7U
+#define PWM_INTR_CH7_Msk (1U << PWM_INTR_CH7_Pos)
+#define PWM_INTR_CH7 PWM_INTR_CH7_Msk
+#define PWM_INTR_CH6_Pos 6U
+#define PWM_INTR_CH6_Msk (1U << PWM_INTR_CH6_Pos)
+#define PWM_INTR_CH6 PWM_INTR_CH6_Msk
+#define PWM_INTR_CH5_Pos 5U
+#define PWM_INTR_CH5_Msk (1U << PWM_INTR_CH5_Pos)
+#define PWM_INTR_CH5 PWM_INTR_CH5_Msk
+#define PWM_INTR_CH4_Pos 4U
+#define PWM_INTR_CH4_Msk (1U << PWM_INTR_CH4_Pos)
+#define PWM_INTR_CH4 PWM_INTR_CH4_Msk
+#define PWM_INTR_CH3_Pos 3U
+#define PWM_INTR_CH3_Msk (1U << PWM_INTR_CH3_Pos)
+#define PWM_INTR_CH3 PWM_INTR_CH3_Msk
+#define PWM_INTR_CH2_Pos 2U
+#define PWM_INTR_CH2_Msk (1U << PWM_INTR_CH2_Pos)
+#define PWM_INTR_CH2 PWM_INTR_CH2_Msk
+#define PWM_INTR_CH1_Pos 1U
+#define PWM_INTR_CH1_Msk (1U << PWM_INTR_CH1_Pos)
+#define PWM_INTR_CH1 PWM_INTR_CH1_Msk
+#define PWM_INTR_CH0_Pos 0U
+#define PWM_INTR_CH0_Msk (1U << PWM_INTR_CH0_Pos)
+#define PWM_INTR_CH0 PWM_INTR_CH0_Msk
+#define PWM_INTR_CH(n) (1U << n)
+
+#define PWM_INTE_CH7_Pos 7U
+#define PWM_INTE_CH7_Msk (1U << PWM_INTE_CH7_Pos)
+#define PWM_INTE_CH7 PWM_INTE_CH7_Msk
+#define PWM_INTE_CH6_Pos 6U
+#define PWM_INTE_CH6_Msk (1U << PWM_INTE_CH6_Pos)
+#define PWM_INTE_CH6 PWM_INTE_CH6_Msk
+#define PWM_INTE_CH5_Pos 5U
+#define PWM_INTE_CH5_Msk (1U << PWM_INTE_CH5_Pos)
+#define PWM_INTE_CH5 PWM_INTE_CH5_Msk
+#define PWM_INTE_CH4_Pos 4U
+#define PWM_INTE_CH4_Msk (1U << PWM_INTE_CH4_Pos)
+#define PWM_INTE_CH4 PWM_INTE_CH4_Msk
+#define PWM_INTE_CH3_Pos 3U
+#define PWM_INTE_CH3_Msk (1U << PWM_INTE_CH3_Pos)
+#define PWM_INTE_CH3 PWM_INTE_CH3_Msk
+#define PWM_INTE_CH2_Pos 2U
+#define PWM_INTE_CH2_Msk (1U << PWM_INTE_CH2_Pos)
+#define PWM_INTE_CH2 PWM_INTE_CH2_Msk
+#define PWM_INTE_CH1_Pos 1U
+#define PWM_INTE_CH1_Msk (1U << PWM_INTE_CH1_Pos)
+#define PWM_INTE_CH1 PWM_INTE_CH1_Msk
+#define PWM_INTE_CH0_Pos 0U
+#define PWM_INTE_CH0_Msk (1U << PWM_INTE_CH0_Pos)
+#define PWM_INTE_CH0 PWM_INTE_CH0_Msk
+#define PWM_INTE_CH(n) (1U << n)
+
+#define PWM_INTF_CH7_Pos 7U
+#define PWM_INTF_CH7_Msk (1U << PWM_INTF_CH7_Pos)
+#define PWM_INTF_CH7 PWM_INTF_CH7_Msk
+#define PWM_INTF_CH6_Pos 6U
+#define PWM_INTF_CH6_Msk (1U << PWM_INTF_CH6_Pos)
+#define PWM_INTF_CH6 PWM_INTF_CH6_Msk
+#define PWM_INTF_CH5_Pos 5U
+#define PWM_INTF_CH5_Msk (1U << PWM_INTF_CH5_Pos)
+#define PWM_INTF_CH5 PWM_INTF_CH5_Msk
+#define PWM_INTF_CH4_Pos 4U
+#define PWM_INTF_CH4_Msk (1U << PWM_INTF_CH4_Pos)
+#define PWM_INTF_CH4 PWM_INTF_CH4_Msk
+#define PWM_INTF_CH3_Pos 3U
+#define PWM_INTF_CH3_Msk (1U << PWM_INTF_CH3_Pos)
+#define PWM_INTF_CH3 PWM_INTF_CH3_Msk
+#define PWM_INTF_CH2_Pos 2U
+#define PWM_INTF_CH2_Msk (1U << PWM_INTF_CH2_Pos)
+#define PWM_INTF_CH2 PWM_INTF_CH2_Msk
+#define PWM_INTF_CH1_Pos 1U
+#define PWM_INTF_CH1_Msk (1U << PWM_INTF_CH1_Pos)
+#define PWM_INTF_CH1 PWM_INTF_CH1_Msk
+#define PWM_INTF_CH0_Pos 0U
+#define PWM_INTF_CH0_Msk (1U << PWM_INTF_CH0_Pos)
+#define PWM_INTF_CH0 PWM_INTF_CH0_Msk
+#define PWM_INTF_CH(n) (1U << n)
+
+#define PWM_INTS_CH7_Pos 7U
+#define PWM_INTS_CH7_Msk (1U << PWM_INTS_CH7_Pos)
+#define PWM_INTS_CH7 PWM_INTS_CH7_Msk
+#define PWM_INTS_CH6_Pos 6U
+#define PWM_INTS_CH6_Msk (1U << PWM_INTS_CH6_Pos)
+#define PWM_INTS_CH6 PWM_INTS_CH6_Msk
+#define PWM_INTS_CH5_Pos 5U
+#define PWM_INTS_CH5_Msk (1U << PWM_INTS_CH5_Pos)
+#define PWM_INTS_CH5 PWM_INTS_CH5_Msk
+#define PWM_INTS_CH4_Pos 4U
+#define PWM_INTS_CH4_Msk (1U << PWM_INTS_CH4_Pos)
+#define PWM_INTS_CH4 PWM_INTS_CH4_Msk
+#define PWM_INTS_CH3_Pos 3U
+#define PWM_INTS_CH3_Msk (1U << PWM_INTS_CH3_Pos)
+#define PWM_INTS_CH3 PWM_INTS_CH3_Msk
+#define PWM_INTS_CH2_Pos 2U
+#define PWM_INTS_CH2_Msk (1U << PWM_INTS_CH2_Pos)
+#define PWM_INTS_CH2 PWM_INTS_CH2_Msk
+#define PWM_INTS_CH1_Pos 1U
+#define PWM_INTS_CH1_Msk (1U << PWM_INTS_CH1_Pos)
+#define PWM_INTS_CH1 PWM_INTS_CH1_Msk
+#define PWM_INTS_CH0_Pos 0U
+#define PWM_INTS_CH0_Msk (1U << PWM_INTS_CH0_Pos)
+#define PWM_INTS_CH0 PWM_INTS_CH0_Msk
+#define PWM_INTS_CH(n) (1U << n)
+/** @} */
#ifdef __cplusplus
extern "C" {
#endif