I am not sure if this is the correct place to ask for assistance but I can not determine what I am doing wrong.
I have not been able to locate an example on using the WSPI driver for QSPI "normal"/arbitrary communication. The only example I can find is the "{ChibiOS}testhal\STM32\multi\WSPI-MFS\" project and this utilizes QSPI through the SNOR driver for either the n25q or the mx25 communicating with wspiCommand and wspiSend.
If you have a simple example demonstrating data operation of the QSPI I would love to try it!
Simplest desired functionality:
Send abritrary data over QSPI following the normal QSPI dataflow: Command, Address, Dummy, Data
Setup:
I am running a version of ChibiOs Trunk from around December 2020, with some patches for some of the LLD's.
But nothing which should impact QSPI.
Board:
Board is a custom layout, but functionality has been verified to work. I have had ChibiOS running multiple threads servicing things such as LWIP ethernet access and SPI connection to the board.
MCU is specifically: STM32H753
The 6 pins used for QSPI has been configured as GPIO and toggled to verify integrity and connections. They are at the moment not connected to anything on the output side.
specific pin configuration can be seen in top part of attached Main() code snippet
Relavant Chibios configs:
mcuconf.h:
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/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 TRUE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 16
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
NOTE: The HCLK which is the clock begin prescaled is running at 80MHz resulting in 5MHz QSPI freq
halconf.h:
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/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI TRUE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
QUADSPIv2 version:
I noticed some posts regarding ISR related issues and HW config bugs so I have updated my QUADSPIv2 to this version which should contain the latest bugfixes:
https://osdn.net/projects/chibios/scm/s ... QUADSPIv2/
Main thread code:
I have made a test main to test the QSPI functionality only running the code in the snippet below
Code: Select all
int main(void)
{
halInit();
OS_API_Init();
palSetPadMode(GPIOB, 2, PAL_MODE_ALTERNATE( 9 ) | PAL_STM32_OSPEED_HIGHEST); //QSPI CLK
palSetPadMode(GPIOG, 6, PAL_MODE_ALTERNATE( 10 ) | PAL_STM32_OSPEED_HIGHEST); //QSPI Chip Select (NCS)
palSetPadMode(GPIOF, 8, PAL_MODE_ALTERNATE( 10 ) | PAL_STM32_OSPEED_HIGHEST); //QSPI IO 0
palSetPadMode(GPIOF, 9, PAL_MODE_ALTERNATE( 10 ) | PAL_STM32_OSPEED_HIGHEST); //QSPI IO 1
palSetPadMode(GPIOF, 7, PAL_MODE_ALTERNATE( 9 ) | PAL_STM32_OSPEED_HIGHEST); //QSPI IO 2
palSetPadMode(GPIOF, 6, PAL_MODE_ALTERNATE( 9 ) | PAL_STM32_OSPEED_HIGHEST); //QSPI IO 3
/* QSPI testing */
static WSPIConfig wcfg;
wspiStart(&WSPID1,&wcfg);
static wspi_command_t cmdp;
cmdp.cfg = (WSPI_CFG_CMD_MODE_FOUR_LINES | \
WSPI_CFG_ADDR_MODE_FOUR_LINES | \
WSPI_CFG_ALT_MODE_NONE | \
WSPI_CFG_DATA_MODE_FOUR_LINES | \
WSPI_CFG_CMD_SIZE_8 | \
WSPI_CFG_ADDR_SIZE_24);
cmdp.addr = 0xFFFFFF;
cmdp.cmd = 0xFF;
cmdp.alt = 0;
cmdp.dummy = 0U;
static uint8_t data_test[10] = {'a'};
while (1)
{
wspiAcquireBus(&WSPID1);
wspiStartCommand(&WSPID1, &cmdp);
wspiStartSend(&WSPID1, &cmdp, 10, data_test);
wspiReleaseBus(&WSPID1);
OS_TaskDelay(100);
}
}
Result:
The code compiles and runs through the loop but nothing is detectable on the pins with a scope.
QSPI Chip Select (NCS) pin remains high and never changes but the rest of the pins are constantly low.
If I use wspiSend() instead the threat is suspended at the line seen below but never wakes up.
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msg = osalThreadSuspendS(&wspip->thread);
Sounds like this old issue: viewtopic.php?t=4289
However "QSPISend()" is not in the driver and I have tested with "wspiSend()"
hypothesis:
Some MCU specific config is incorrectly setup?
- ITR?
- MDMA config / Handling?
I may have forgotten some specific WSPI configuration?
- Command config?
- WSPI start config?
This can for some reason not be done from main threat?
Do you have any idea about what might be the issue?