STM SDMMCv2 clock div Topic is solved

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tmentink
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STM SDMMCv2 clock div  Topic is solved

Postby tmentink » Tue Jun 01, 2021 7:02 pm

Hi,

The current implementation of the STM SDMMCv2 has an bug with the clock divider

Code: Select all

void sdc_lld_start_clk(SDCDriver *sdcp) {

  /* Initial clock setting: 400kHz, 1bit mode.*/
  sdcp->sdmmc->CLKCR  = sdc_lld_clkdiv(sdcp, 4000000);
 


The 4000000 has one zero too many. Therefore the clock is not divided to 400Khz, but to 4Mhz.

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Re: STM SDMMCv2 clock div

Postby Giovanni » Tue Jun 01, 2021 8:17 pm

Thanks for finding.

Giovanni

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Re: STM SDMMCv2 clock div

Postby Giovanni » Sun Jun 13, 2021 1:40 pm

Fixed as bug #1160.

Giovanni


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