Cache-related problem in some STM32 HAL drivers

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Giovanni
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Cache-related problem in some STM32 HAL drivers

Postby Giovanni » Sun Mar 17, 2019 9:17 am

Hi,

Putting this here to keep track.

Several LLDs have DMA-accessible buffers inside the driver structure, this is a problem on those devices where cache coherency must be handled.

Required action: move all buffers outside the driver structure, replace those with a pointer to the actual buffer which should be aligned to cache lines.

Giovanni

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Re: Cache-related problem in some STM32 HAL drivers

Postby Giovanni » Sun Nov 10, 2019 10:22 am

bump

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Re: Cache-related problem in some STM32 HAL drivers

Postby faisal » Mon Mar 17, 2025 1:55 pm

Has this been addressed? If so, in what versions?

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Re: Cache-related problem in some STM32 HAL drivers

Postby Giovanni » Mon Mar 17, 2025 2:54 pm

This has been addressed for SNOR, now XSNOR. I need to check sd_mmc but I think it was addressed there too.

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Re: Cache-related problem in some STM32 HAL drivers

Postby FXCoder » Tue Mar 18, 2025 2:16 am

Addressed the SPI dummy variables as well by allowing the entire driver structure to be located in non-cache.
Drivers now have this for allocation...

Code: Select all

/** @brief SPI1 driver identifier.*/
#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
SPI_SPID1_MEMORY SPIDriver SPID1;
#endif

So just define the non-cache section to be used.


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