Hi,
Putting this here to keep track.
Several LLDs have DMA-accessible buffers inside the driver structure, this is a problem on those devices where cache coherency must be handled.
Required action: move all buffers outside the driver structure, replace those with a pointer to the actual buffer which should be aligned to cache lines.
Giovanni
Cache-related problem in some STM32 HAL drivers
- Giovanni
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- Giovanni
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- Giovanni
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Re: Cache-related problem in some STM32 HAL drivers
This has been addressed for SNOR, now XSNOR. I need to check sd_mmc but I think it was addressed there too.
Giovanni
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Re: Cache-related problem in some STM32 HAL drivers
Addressed the SPI dummy variables as well by allowing the entire driver structure to be located in non-cache.
Drivers now have this for allocation...
So just define the non-cache section to be used.
Drivers now have this for allocation...
Code: Select all
/** @brief SPI1 driver identifier.*/
#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
SPI_SPID1_MEMORY SPIDriver SPID1;
#endif
So just define the non-cache section to be used.
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