Posting this as noted from post viewtopic.php?f=16&p=43440#p43440
Update of STM32C0xx port files, implementing missing code for USB (and CRC) related code, as well a change in the mcuconf.h file of the RT-STM32C071RB-NUCLEO64 demo (STM32_USB_USB1_LP_IRQ_PRIORITY).
These changes are based on the STM32G0xx port files, and I validated the registers related to the code with both STM32C071RB and STM32G0B1RE reference manuals (both includes USB).
Code: Select all
From b3967dee62c0cac41de658056a16e077d8256b64 Mon Sep 17 00:00:00 2001
From: engemil <engemil@users.noreply.github.com>
Date: Tue, 19 Aug 2025 22:57:09 +0200
Subject: [PATCH] Added missing USB port for STM32C071RB (STM32C0xx port), and
corrected USB IQR priority for STM32C071RB demo mcu config file
---
.../RT-STM32C071RB-NUCLEO64/cfg/mcuconf.h | 2 +-
os/hal/ports/STM32/STM32C0xx/stm32_isr.h | 8 +++
os/hal/ports/STM32/STM32C0xx/stm32_rcc.h | 56 +++++++++++++++++++
3 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/demos/STM32/RT-STM32C071RB-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32C071RB-NUCLEO64/cfg/mcuconf.h
index 0e69ec24fb..3719c3ebed 100644
--- a/demos/STM32/RT-STM32C071RB-NUCLEO64/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32C071RB-NUCLEO64/cfg/mcuconf.h
@@ -188,7 +188,7 @@
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 FALSE
-#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
+#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
#define STM32_USB_USE_ISOCHRONOUS FALSE
#define STM32_USB_USE_FAST_COPY FALSE
#define STM32_USB_HOST_WAKEUP_DURATION 2
diff --git a/os/hal/ports/STM32/STM32C0xx/stm32_isr.h b/os/hal/ports/STM32/STM32C0xx/stm32_isr.h
index dcd7ce316e..aa5516f815 100644
--- a/os/hal/ports/STM32/STM32C0xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32C0xx/stm32_isr.h
@@ -126,6 +126,14 @@
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER Vector60
+#define STM32_USB1_LP_HANDLER Vector60
+#define STM32_USB1_HP_NUMBER 8
+#define STM32_USB1_LP_NUMBER 8
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
index d88307d4ef..29c521b55c 100644
--- a/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
@@ -608,6 +608,62 @@
#define rccResetUSART2() rccResetAPBR1(RCC_APBRSTR1_USART2RST)
/** @} */
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPBR1(RCC_APBENR1_USBEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSB() rccDisableAPBR1(RCC_APBENR1_USBEN)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPBR1(RCC_APBRSTR1_USBRST)
+/** @} */
+
+/**
+ * @name CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
+
+/**
+ * @brief Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
+/** @} */
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
