STM32F411xC/E: Wrong entries in PLLI2SCFGR

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STM32F411xC/E: Wrong entries in PLLI2SCFGR

Postby WowSuchName » Thu Nov 26, 2020 10:59 pm

Hi,

the current LLD implementation for the STM32F4 family does not support the I2S PLL on the STM32F411xC/E (and presumably others).

- ChibiOS version
20.3.2 (as of the tag ver20.3.2 on the github mirror)

- Compiler
gcc version 10.2.0 (Arch Repository)

- Platform and board
STM32F411VET6 on the STM32F411-DISCO (*not* STM32F4-DISCO)

- Natur of the problem
The STM32F411xC/E series controller (and presumably others) have a different configuration than implemented in the I2S hal, which I assume to be tailored to another STM32F4 series (e.g. [2]?).

Some differences as compared to the RCC_I2SPLLCFGR setup (os/hal/ports/STM32/STM32F4xx/hal_lld.c:238):
- The 411 series features a dedicated input divider M for the I2S PLL,
- it lacks the output divider Q, and
- probably many more,
see [1, p. 93/844].

- Failure mode

The controller does not start up, as it waits for the I2S pll which is configured for the wrong controller.



Thanks in advance!

Best regards
Tim


References:

[1] ST RM0383 Reference manual: STM32F411xC/E advanced Arm®-based 32-bit MCUs
[2] ST RM0090 Reference manual: STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 advanced Arm®-based 32-bit MCUs

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Re: STM32F411xC/E: Wrong entries in PLLI2SCFGR

Postby Giovanni » Tue Apr 04, 2023 2:48 pm

Leaving a note here.

This requires a separate clock tree "type", closest one is F413, which has the separated M divider also. F413 has a lot of extra dividers and muxes but the common part looks equal, this new header could be obtained by stripping the F413 one of extra settings.

Giovanni


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