The current implementation of the STM SDMMCv2 has an bug with the clock divider
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void sdc_lld_start_clk(SDCDriver *sdcp) {
/* Initial clock setting: 400kHz, 1bit mode.*/
sdcp->sdmmc->CLKCR = sdc_lld_clkdiv(sdcp, 4000000);
The 4000000 has one zero too many. Therefore the clock is not divided to 400Khz, but to 4Mhz.