SDC bus speed

[tmentink]

Hi,

While running the SdcConnect function on an STM32L4+ & EMMC, the bus speed is switched to a high speed

Code: Select all

 /* Switches to high speed.*/
  if (HAL_SUCCESS != detect_bus_clk(sdcp, &clk)) {
    goto failed;
  }
  sdc_lld_set_data_clk(sdcp, clk);
 

In the function sdc_lld_set_data_clk, the clock will be set to the correct bus speed. This function fails because it is blocked by the ST hardware. So the value will not change.
After this function the connection fails, probably due to incorrect clock settings on both ends.

I moved the code above to a later position in the SdcConnect function

Code: Select all

  /* Switches to high speed.*/
  if (HAL_SUCCESS != detect_bus_clk(sdcp, &clk)) {
    goto failed;
  }
  sdc_lld_set_data_clk(sdcp, clk);


  /* Initialization complete.*/
  sdcp->state = BLK_READY;
  return HAL_SUCCESS; 
 

Now the STM connects correctly to my EMMC and is the clock set correctly.

I don`t know if this is only an issue with the STM32L4+ as this is a high level SDC function

[Giovanni]

Not sure about this one, perhaps moving that code is just changing timings enough to hide a race condition.

Could you try compiling with no optimizations? -O0, if it is a race condition this could make the problem disappear, then the solution would be adding a proper delay somewhere in the LLD.

Giovanni

[tmentink]

Tried compiling it with no optimalisations, but no luck.
Maybe the Bus is still working on a message that is transmitting. I will try to add a while loop to check if I can write the clock value.

[Giovanni]

Any news?

Giovanni

[tmentink]

Hi,

I cannot find any solution to this problem. The DPSMACT bit is set in the SDMMC_STAR Register (Bit 12 DPSMACT: Data path state machine active, i.e. not in Idle state) This bit is set after writing the "Detect_bus_clk" function. This bit is however not set if I apply my "fix"

[Giovanni]

bumping as self-reminder

unable to test this