e200 broken in 21.6.x

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mobyfab
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e200 broken in 21.6.x

Postby mobyfab » Tue Sep 21, 2021 10:41 pm

It seems like the latest release broke compatibility.
I'm using freescale's ppc vle gcc (4.9.4)

Code: Select all

../../../os/rt/src/chinstances.c: In function 'chInstanceObjectInit':
../../../os/rt/src/chinstances.c:109:3: error: too many arguments to function 'port_init'
   port_init(oip);
   ^
In file included from ../../../os/rt/include/chport.h:37:0,
                 from ../../../os/rt/include/ch.h:106,
                 from ../../../os/rt/src/chinstances.c:29:
../../../os/common/ports/e200/chcore.h:508:20: note: declared here
 static inline void port_init(void) {
                    ^
make: *** [../../../os/common/startup/e200/compilers/GCC/rules.mk:162: build/obj/chinstances.o] Error 1

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Re: e200 broken in 21.6.x

Postby Giovanni » Wed Sep 22, 2021 5:26 am

Hi,

Is there a Linux version of the compiler? We could add to the CI server.

Giovanni

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Re: e200 broken in 21.6.x

Postby mobyfab » Wed Sep 22, 2021 10:06 am

yes, it's bundled with S32DS Linux

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Re: e200 broken in 21.6.x

Postby Giovanni » Wed Sep 22, 2021 10:32 am

mobyfab wrote:yes, it's bundled with S32DS Linux


Thanks, I just need the compiler but I will give it a try.

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Re: e200 broken in 21.6.x

Postby mobyfab » Sat Sep 25, 2021 11:54 pm

I've made a script to build the toolchain with their patches

https://github.com/fpoussin/gcc-powerpc-eabivle

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Re: e200 broken in 21.6.x

Postby Giovanni » Sun Sep 26, 2021 5:16 pm

Hi,

The script worked flawlessly, thanks.

The compiler worked but linker fails this way:

Code: Select all

/home/giovanni/Projects/ChibiStudio/tools/cross-powerpc-eabivle/bin/../lib/gcc/powerpc-eabivle/4.9.4/libgcc.a(eabivle.o): In function `__eabi':
/home/giovanni/Projects/gcc-powerpc-eabivle-master/build-gcc/powerpc-eabivle/libgcc/../../../extracted/gcc-4.9.4/libgcc/config/rs6000/eabivle.S:328: undefined reference to `__init'
/home/giovanni/Projects/ChibiStudio/tools/cross-powerpc-eabivle/bin/../lib/gcc/powerpc-eabivle/4.9.4/libgcc.a(eabivle.o):(.got2+0x8): undefined reference to `__SDATA_START__'
/home/giovanni/Projects/ChibiStudio/tools/cross-powerpc-eabivle/bin/../lib/gcc/powerpc-eabivle/4.9.4/libgcc.a(eabivle.o):(.got2+0xc): undefined reference to `__SBSS_END__'
/home/giovanni/Projects/ChibiStudio/tools/cross-powerpc-eabivle/bin/../lib/gcc/powerpc-eabivle/4.9.4/libgcc.a(eabivle.o):(.got2+0x14): undefined reference to `__SDATA2_START__'
/home/giovanni/Projects/ChibiStudio/tools/cross-powerpc-eabivle/bin/../lib/gcc/powerpc-eabivle/4.9.4/libgcc.a(eabivle.o):(.got2+0x18): undefined reference to `__SBSS2_END__'


Apparently the library has different requirements compared to the GCC I used to use. I imagine the NXP compiler would give the same errors, not sure how to address the __init symbol (others are clear enough), I imagine it is a function to be implemented, what is supposed to do?

I fixed the problem you mentioned in trunk (will make sure it is in all branches).

Giovanni

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Re: e200 broken in 21.6.x

Postby mobyfab » Sun Sep 26, 2021 7:30 pm

I've just updated the script with GDB

I'm having the same linker issue, it's caused by one of the vle patches I think:
https://github.com/fpoussin/gcc-powerpc ... tch#L10769
https://github.com/fpoussin/gcc-powerpc ... tch#L10858

I suspect S32DS to have these aliases defined somewhere
Last edited by mobyfab on Sun Sep 26, 2021 7:43 pm, edited 2 times in total.

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Re: e200 broken in 21.6.x

Postby Giovanni » Sun Sep 26, 2021 7:39 pm

Hi,

I found an older version 4.9.2 and it does not fail because those externals, the library directory contains multiple versions of the library for the various cores and with/without FP support but I don't see anything about those externals, perhaps something is added inside libraries or it is an older library version.

/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/e200z0
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/e200z2
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/e200z3
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/e200z4
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/e200z6
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/e200z7
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/fp
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/include
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/include-fixed
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/install-tools
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/plugin
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/spe
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/crtbegin.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/crtbeginS.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/crtbeginT.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/crtend.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/crtendS.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/ecrti.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/ecrtn.o
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/libgcc.a
/home/giovanni/Projects/ChibiStudio/tools/powerpc-eabivle/lib/gcc/powerpc-eabivle/4.9.2/libgcov.a

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Re: e200 broken in 21.6.x

Postby mobyfab » Sun Sep 26, 2021 7:43 pm

here is an example linker + startup file from S32DS but I don't see this __init function

Code: Select all

/* Entry Point */
ENTRY(_start)

/* define heap and stack size */
__HEAP_SIZE            = 0 ;
__STACK_SIZE           = 4096 ;

SRAM_SIZE =  128K;   
/* Define SRAM Base Address */
SRAM_BASE_ADDR = 0x40000000;
   
MEMORY
{

    flash_rchw : org = 0x00000000,   len = 0x08
       
    m_text :   org = 0x1000, len = 1022K 
    m_data :   org = 0x40000000,   len = 128K
       
}


SECTIONS
{
    .rchw   :
    {
        KEEP(*(.rchw))
    } > flash_rchw

    .startup : ALIGN(0x400)
    {
    __start = . ;
       *(.startup)
    } > m_text
   
    .core_exceptions_table   : ALIGN(0x1000)
    {
      __IVPR_VALUE = . ;
      KEEP(*(.core_exceptions_table))
    } > m_text

    .intc_vector_table   : ALIGN(0x1000) 
    {
      KEEP(*(.intc_vector_table))
    } > m_text
     
    .text_booke :
    {
      INPUT_SECTION_FLAGS (!SHF_PPC_VLE)
      *(.text*)     
    } > m_text           
           
    .text_vle :
    { INPUT_SECTION_FLAGS (SHF_PPC_VLE)
      *(.text.startup)
      *(.text)     
      *(.text.*)
      KEEP (*(.init))
      KEEP (*(.fini))           
      . = ALIGN(16);     
    } > m_text       /* that will force pick VLE .text sections */
       
    .ctors :
    {
      __CTOR_LIST__ = .;
      /* gcc uses crtbegin.o to find the start of
         the constructors, so we make sure it is
         first.  Because this is a wildcard, it
         doesn't matter if the user does not
         actually link against crtbegin.o; the
         linker won't look for a file to match a
         wildcard.  The wildcard also means that it
         doesn't matter which directory crtbegin.o
         is in.  */
      KEEP (*crtbegin.o(.ctors))
      KEEP (*crtbegin?.o(.ctors))
      /* We don't want to include the .ctor section from
         from the crtend.o file until after the sorted ctors.
         The .ctor section from the crtend file contains the
         end of ctors marker and it must be last */
      KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
      KEEP (*(SORT(.ctors.*)))
      KEEP (*(.ctors))
      __CTOR_END__ = .;
    } > m_text

    .dtors :
    {
      __DTOR_LIST__ = .;
      KEEP (*crtbegin.o(.dtors))
      KEEP (*crtbegin?.o(.dtors))
      KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
      KEEP (*(SORT(.dtors.*)))
      KEEP (*(.dtors))
      __DTOR_END__ = .;
    } > m_text
       
    .preinit_array :
    {
      PROVIDE_HIDDEN (__preinit_array_start = .);
      KEEP (*(.preinit_array*))
      PROVIDE_HIDDEN (__preinit_array_end = .);
    } > m_text

    .init_array :
    {
      PROVIDE_HIDDEN (__init_array_start = .);
      KEEP (*(SORT(.init_array.*)))
      KEEP (*(.init_array*))
      PROVIDE_HIDDEN (__init_array_end = .);
    } > m_text

    .fini_array :
    {
      PROVIDE_HIDDEN (__fini_array_start = .);
      KEEP (*(SORT(.fini_array.*)))
      KEEP (*(.fini_array*))
      PROVIDE_HIDDEN (__fini_array_end = .);
    } > m_text
         
    .rodata :
    {
      *(.rodata)
      *(.rodata.*)
    } > m_text
   
    .eh_frame_hdr : { *(.eh_frame_hdr) } > m_text
    .eh_frame     : { KEEP (*(.eh_frame)) } > m_text
   
    .data   :
    {
      *(.data)
      *(.data.*)
    }  > m_data AT>m_text
   
    .sdata2  :
    { 
      *(.sdata2)
      *(.sdata2.*)
    } > m_data AT>m_text

    .sbss2    (NOLOAD)   :
    {
      /* _SDA2_BASE_ = .; */
      *(.sbss2)
      *(.sbss2.*)
    } > m_data
   
    .sdata  :
    {
      *(.sdata)
      *(.sdata.*)
    } > m_data AT>m_text
   
    .bss   (NOLOAD)  :
    {
      __BSS_START = .;
      *(.sbss)
      *(.sbss.*)   
      *(.bss)
      *(.bss.*)
      *(COMMON)
      __BSS_END = .;
    } > m_data
   
    .stack (NOLOAD) : ALIGN(16)
    {
      __HEAP = . ;
      PROVIDE (_end = . );
      PROVIDE (end = . );           
      . += __HEAP_SIZE ;
      __HEAP_END = . ;
      _stack_end = . ;
      . +=  __STACK_SIZE ;
      _stack_addr = . ;
      __SP_INIT = . ;
      . += 4;
    } > m_data
 
/*-------- LABELS USED IN CODE -------------------------------*/
       
/* Labels for Copying Initialised Data from Flash to RAM */
__DATA_SRAM_ADDR  = ADDR(.data);
__SDATA_SRAM_ADDR = ADDR(.sdata);

__DATA_SIZE   = SIZEOF(.data);
__SDATA_SIZE  = SIZEOF(.sdata);

__DATA_ROM_ADDR  = LOADADDR(.data);
__SDATA_ROM_ADDR = LOADADDR(.sdata);
   
/* Labels Used for Initialising SRAM ECC */
__SRAM_SIZE = SRAM_SIZE;
__SRAM_BASE_ADDR = SRAM_BASE_ADDR;
     
__BSS_SIZE    = __BSS_END - __BSS_START;

}



init code

Code: Select all

#define ICACHE_ENABLE 0
#define DCACHE_ENABLE 0

#ifdef __ghs__    /* GreenHills */
        .section    .startup, axv
      .vle

        .align 3  ;# 8 bytes

      .extern   main
      .extern __SRAM_SIZE
      .extern __SRAM_BASE_ADDR
      .extern __DATA_SIZE
      .extern __DATA_ROM_ADDR
      .extern __DATA_SRAM_ADDR
      .extern __SDATA_SIZE
      .extern __SDATA_ROM_ADDR
      .extern __SDATA_SRAM_ADDR
      .extern __BSS_START
        .extern __BSS_END
        .extern __BSS_SIZE
      .extern __SP_INIT
      .extern _SDA_BASE_
      .extern _SDA2_BASE_
#endif
#ifdef __GNUC__   /* GCC */
      .section .startup, "ax"
#endif

#ifdef __DCC__ /* Diab */
       .section ".startup",4,rx       
#endif
        .globl   _start

_start:
      e_nop

#if defined(MMU_CONFIG)

#if defined(__GNUC__)
   #define param(p) \p
   .macro spr opcode, val
        e_lis   r10, \val@h
        e_or2i   r10, \val@l
        \opcode r10
   .endm
#elif defined (__DCC__) || defined (__ghs__)
   #define param(p) p
   .macro spr opcode, val
        e_lis   r10, val@h
        e_or2i   r10, val@l
        opcode r10
   .endm
#else
   #error "Compiler is not supported"
#endif

  .macro mmu_entry val0, val1, val2, val3
      spr mtmas0, param(val0)
      spr mtmas1, param(val1)
      spr mtmas2, param(val2)
      spr mtmas3, param(val3)
        tlbwe
 .endm

#if defined(MPC563xM)
      mmu_entry   0x10000000, 0xC0000500, 0xFFF0002A, 0xFFF0003F // Setup MMU for for Periph B Modules
      mmu_entry   0x10030000, 0xC0000400, 0x40000028, 0x4000003F // Set up MMU for Internal SRAM
      mmu_entry   0x10040000, 0xC0000500, 0xC3F0002A, 0xC3F0003F // Setup MMU for Periph A Modules
      mmu_entry   0x10020000, 0xC0000700, 0x20000020, 0x2000003F // Setup MMU for External Memory
      mmu_entry   0x10010000, 0xC0000700, 0x00000020, 0x0000003F // Setup MMU for Internal Flash
      mmu_entry   0x10050000, 0xC0000600, 0x3FC00020, 0x3FC0003F // Set up MMU for External SRAM
#elif defined(MPC564xB) || defined(MPC564xL) || defined(MPC567xK)
;# Set up MMU
;#  MAS0 : ESEL=1
;#  MAS1 : TSIZ=1Gbytes
;#  MAS2 : EPN=0x400000000, W=0, I=1, M=0, G=0, E=big
;#  MAS3 : RPN=0x400000000, PERMIS=all */
      e_lis   r3, 0x1001
      mtspr   624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0A00
      mtspr   625,  r4

      e_lis   r5, 0x4000
      e_or2i  r5, 0x0028
      mtspr   626, r5

      e_lis  r6, 0x4000
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe

;# MAS0 : ESEL=0
;# MAS1 : TSIZ=16Mbytes
;# MAS2 : EPN=0x000000000, VLE=1, W=0, I=0, M=0, G=0, E=big
;# MAS3 : RPN=0x000000000, PERMIS=all */
      e_lis   r3, 0x1000
      mtspr   624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0700
      mtspr   625, r4

      e_lis   r5, 0x0000
      e_or2i  r5, 0x0020
      mtspr   626, r5

      e_lis  r6,0x0000
      e_or2i r6, 0x003f
      mtspr  627, r6

      msync        ;# Synchronize for running out of flash
      tlbwe
      se_isync     ;# Synchronize for running out of flash

;#  MAS0 : ESEL=2
;#  MAS1 : TSIZ=1Gbytes
;#  MAS2 : EPN=0xC00000000, W=0, I=1, M=0, G=1, E=big
;#  MAS3 : RPN=0xC00000000, PERMIS=all */
      e_lis   r3, 0x1002
      mtspr   624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0A00
      mtspr   625, r4

      e_lis  r5, 0xC000
      e_or2i r5, 0x000A
      mtspr  626, r5

      e_lis  r6,0xC000
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe
#endif /* defined(MPC564xB) || defined(MPC564xL) || defined(MPC567xK) */
#endif /* defined(MMU_CONFIG) */

#if defined(MPC567xR)
;# Set up MMU
#ifndef START_FROM_FLASH
      e_lis   r3, 0x1001
      mtspr  624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0480
      mtspr  625,  r4

      e_lis   r5, 0x4000
      e_or2i  r5, 0x0028
      mtspr  626, r5

      e_lis  r6, 0x4000
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe
#endif

      e_lis   r3, 0x1002
      mtspr  624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0580
      mtspr  625,  r4

      e_lis   r5, 0xFFE0
      e_or2i  r5, 0x002A
      mtspr  626, r5

      e_lis  r6, 0xFFE0
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe

      e_lis   r3, 0x1000
      mtspr  624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0700
      mtspr  625, r4

      e_lis   r5, 0x0000
      e_or2i  r5, 0x0020
      mtspr  626, r5

      e_lis  r6,0x0000
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe

      e_lis   r3, 0x1003
      mtspr  624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0700
      mtspr  625, r4

      e_lis   r5, 0x2000
      e_or2i  r5, 0x0020
      mtspr  626, r5

      e_lis  r6,0x0000
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe

#ifdef START_FROM_FLASH
      e_lis   r3, 0x1001
      mtspr  624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0480
      mtspr  625,  r4

      e_lis   r5, 0x4000
      e_or2i  r5, 0x0028
      mtspr  626, r5

      e_lis  r6, 0x4000
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe
#endif

      e_lis   r3, 0x1004
      mtspr  624, r3

      e_lis   r4, 0xC000
      e_or2i  r4, 0x0580
      mtspr  625,  r4

      e_lis   r5, 0xC3E0
      e_or2i  r5, 0x002A
      mtspr  626, r5

      e_lis  r6, 0xC3E0
      e_or2i r6, 0x003f
      mtspr  627, r6

      tlbwe
#endif /* if defined(MPC567xR) */

#if defined(DISABLE_SWT)
;#****************************** Turn off SWT ********************************
      e_lis   r4, 0xFFF3
      e_or2i   r4, 0x8000

      e_li   r3, 0xC520
      e_stw   r3, 0x10(r4)

      e_li   r3, 0xD928
      e_stw   r3, 0x10(r4)

      e_lis   r3, 0xFF00
      e_or2i   r3, 0x010A
      e_stw   r3, 0(r4)
#endif

;#********************************* Enable BTB ********************************
;# Flush & Enable BTB - Set BBFI bit in BUCSR
      e_li   r3, 0x201
      mtspr   1013, r3
      se_isync

#if defined (E200Z4) || defined(E200Z7)
;#**************************** Init Core Registers ****************************
;# The E200Z4 core needs its registers initialising before they are used
;# otherwise in Lock Step mode the two cores will contain different random data.
;# If this is stored to memory (e.g. stacked) it will cause a Lock Step error.

;# GPRs 0-31
      e_li   r0, 0
      e_li   r1, 0
      e_li   r2, 0
      e_li   r3, 0
      e_li   r4, 0
      e_li   r5, 0
      e_li   r6, 0
      e_li   r7, 0
      e_li   r8, 0
      e_li   r9, 0
      e_li   r10, 0
      e_li   r11, 0
      e_li   r12, 0
      e_li   r13, 0
      e_li   r14, 0
      e_li   r15, 0
      e_li   r16, 0
      e_li   r17, 0
      e_li   r18, 0
      e_li   r19, 0
      e_li   r20, 0
      e_li   r21, 0
      e_li   r22, 0
      e_li   r23, 0
      e_li   r24, 0
      e_li   r25, 0
      e_li   r26, 0
      e_li   r27, 0
      e_li   r28, 0
      e_li   r29, 0
      e_li   r30, 0
      e_li   r31, 0

;# Init any other CPU register which might be stacked (before being used).

      mtspr   1, r1      ;#XER
       mtcrf   0xFF, r1
       mtspr   CTR, r1
      mtspr   272, r1      ;#SPRG0
      mtspr   273, r1      ;#SPRG1
      mtspr   274, r1      ;#SPRG2
      mtspr   275, r1      ;#SPRG3
      mtspr   58, r1      ;#CSRR0
      mtspr   59, r1      ;#CSRR1
      mtspr   570, r1      ;#MCSRR0
      mtspr   571, r1      ;#MCSRR1
      mtspr   61, r1      ;#DEAR
      mtspr   63, r1      ;#IVPR
      mtspr   256, r1      ;#USPRG0
      mtspr   62, r1      ;#ESR
      mtspr   8, r31      ;#LR
#endif

#ifdef START_FROM_FLASH
;#***************************** Initialise SRAM ECC ***************************/
;# Store number of 128Byte (32GPRs) segments in Counter
 e_lis       r5, __SRAM_SIZE@h  # Initialize r5 to size of SRAM (Bytes)
 e_or2i      r5, __SRAM_SIZE@l
 e_srwi      r5, r5, 0x7         # Divide SRAM size by 128
 mtctr       r5                  # Move to counter for use with "bdnz"

;# Base Address of the internal SRAM
 e_lis       r5, __SRAM_BASE_ADDR@h
 e_or2i      r5, __SRAM_BASE_ADDR@l

;# Fill SRAM with writes of 32GPRs
sram_loop:
    e_stmw      r0,0(r5)            # Write all 32 registers to SRAM
    e_addi      r5,r5,128           # Increment the RAM pointer to next 128bytes
    e_bdnz      sram_loop           # Loop for all of SRAM

   
;#*************** Load Initialised Data Values from Flash into RAM ************/
;# Initialised Data - ".data"
DATACOPY:
    e_lis       r9, __DATA_SIZE@ha      # Load upper SRAM load size (# of bytes) into R9
    e_or2i      r9, __DATA_SIZE@l       # Load lower SRAM load size into R9                                     
    e_cmp16i    r9,0                    # Compare to see if equal to 0                                 
    e_beq       SDATACOPY               # Exit cfg_ROMCPY if size is zero (no data to initialise)
                                       
    mtctr       r9                      # Store no. of bytes to be moved in counter
                                       
    e_lis       r10, __DATA_ROM_ADDR@h  # Load address of first SRAM load into R10
    e_or2i      r10, __DATA_ROM_ADDR@l  # Load lower address of SRAM load into R10
    e_subi      r10,r10, 1              # Decrement address to prepare for ROMCPYLOOP

    e_lis       r5, __DATA_SRAM_ADDR@h  # Load upper SRAM address into R5 (from linker file)
    e_or2i      r5, __DATA_SRAM_ADDR@l  # Load lower SRAM address into R5 (from linker file)
    e_subi      r5, r5, 1               # Decrement address to prepare for ROMCPYLOOP

DATACPYLOOP:
    e_lbzu      r4, 1(r10)              # Load data byte at R10 into R4,incrementing (update) ROM address
    e_stbu      r4, 1(r5)               # Store R4 data byte into SRAM at R5 and update SRAM address
    e_bdnz      DATACPYLOOP             # Branch if more bytes to load from ROM

;# Small Initialised Data - ".sdata"
SDATACOPY:   
    e_lis       r9, __SDATA_SIZE@ha     # Load upper SRAM load size (# of bytes) into R9
    e_or2i      r9, __SDATA_SIZE@l      # Load lower SRAM load size into R9                                     
    e_cmp16i    r9,0                    # Compare to see if equal to 0                                 
    e_beq       ROMCPYEND               # Exit cfg_ROMCPY if size is zero (no data to initialise)
                                       
    mtctr       r9                      # Store no. of bytes to be moved in counter
                                       
    e_lis       r10, __SDATA_ROM_ADDR@h # Load address of first SRAM load into R10
    e_or2i      r10, __SDATA_ROM_ADDR@l # Load lower address of SRAM load into R10
    e_subi      r10,r10, 1              # Decrement address to prepare for ROMCPYLOOP

    e_lis       r5, __SDATA_SRAM_ADDR@h # Load upper SRAM address into R5 (from linker file)
    e_or2i      r5, __SDATA_SRAM_ADDR@l # Load lower SRAM address into R5 (from linker file)
    e_subi      r5, r5, 1               # Decrement address to prepare for ROMCPYLOOP

SDATACPYLOOP:
    e_lbzu      r4, 1(r10)              # Load data byte at R10 into R4,incrementing (update) ROM address
    e_stbu      r4, 1(r5)               # Store R4 data byte into SRAM at R5 and update SRAM address
    e_bdnz      SDATACPYLOOP            # Branch if more bytes to load from ROM
   
   
ROMCPYEND:
#endif

;#*************************** Enable ME Bit in MSR *****************************
      mfmsr   r6
      e_or2i   r6,0x1000
      mtmsr   r6

#if defined(SPE_ENABLE)
;#*************************** Enable SPE Bit in MSR *****************************
      mfmsr r3
      e_or2is r3,0x0200
      mtmsr r3
#endif

#if defined(I_CACHE) && (ICACHE_ENABLE == 1)
;#****************** Invalidate and Enable the Instruction cache **************
__icache_cfg:
      e_li   r5, 0x2
      mtspr   1011,r5

      e_li   r7, 0x4
      e_li   r8, 0x2
      ;#e_lwi r11, 0xFFFFFFFB
      e_lis   r11,0xFFFF
      e_or2i   r11,0xFFFB

__icache_inv:
      mfspr   r9, 1011
      and.   r10, r7, r9
      e_beq   __icache_no_abort
      and.   r10, r11, r9
      mtspr   1011, r10
      e_b      __icache_cfg

__icache_no_abort:
      and.   r10, r8, r9
      e_bne   __icache_inv

      mfspr   r5, 1011
      e_ori   r5, r5, 0x0001
      se_isync
      ;#msync
      mtspr   1011, r5
#endif

#if defined(D_CACHE) && (DCACHE_ENABLE == 1)
;#****************** Invalidate and Enable the Data cache **************
__dcache_cfg:
      e_li r5, 0x2
      mtspr 1010,r5

      e_li r7, 0x4
      e_li r8, 0x2
      e_lis   r11,0xFFFF
      e_or2i   r11,0xFFFB

__dcache_inv:
      mfspr r9, 1010
      and.  r10, r7, r9
      e_beq   __dcache_no_abort
      and.  r10, r11, r9
      mtspr 1010, r10
      e_b __dcache_cfg

__dcache_no_abort:
      and.  r10, r8, r9
      e_bne __dcache_inv

      mfspr r5, 1010
      e_ori   r5, r5, 0x0001
      se_isync
      msync
      mtspr 1010, r5
#endif

;#****************************** Initialize BSS section ******************************/
bss_Init:
    e_lis        r9, __BSS_SIZE@h       # Load upper BSS load size (# of bytes) into R9
    e_or2i       r9, __BSS_SIZE@l       # Load lower BSS load size into R9 and compare to zero
    e_cmp16i     r9,0
    e_beq        bss_Init_end           # Exit if size is zero (no data to initialise)

    mtctr        r9                     # Store no. of bytes to be moved in counter

    e_lis        r5, __BSS_START@h      # Load upper BSS address into R5 (from linker file)
    e_or2i       r5, __BSS_START@l      # Load lower BSS address into R5 (from linker file)
    e_subi       r5, r5, 1              # Decrement address to prepare for bss_Init_loop

    e_lis        r4, 0x0

bss_Init_loop:
    e_stbu       r4, 1(r5)              # Store zero byte into BSS at R5 and update BSS address
    e_bdnz       bss_Init_loop          # Branch if more bytes to load

bss_Init_end:

;#****************************** Configure Stack ******************************/
      e_lis   r1, __SP_INIT@h   ;# Initialize stack pointer r1 to
      e_or2i   r1, __SP_INIT@l   ;# value in linker command file.

      e_lis   r13, _SDA_BASE_@h   ;# Initialize r13 to sdata base
      e_or2i   r13, _SDA_BASE_@l   ;# (provided by linker).

      e_lis   r2, _SDA2_BASE_@h   ;# Initialize r2 to sdata2 base
      e_or2i   r2, _SDA2_BASE_@l   ;# (provided by linker).

      e_stwu   r0,-64(r1)         ;# Terminate stack.

#if defined(HW_INIT)
;# perform hardware init prior to main
      e_bl   hw_init
#endif

#ifdef __DCC__ /* Diab */
      e_bl   __init_main
#endif

;# Jump to Main
      e_bl   main

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Giovanni
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Re: e200 broken in 21.6.x

Postby Giovanni » Sun Sep 26, 2021 8:05 pm

It is called by __eabi() which I am not sure where is called from library.

Found it mentioned: https://gcc.gnu.org/legacy-ml/gcc-help/ ... 00199.html

Giovanni


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