i was stumbling over the errata sheet of STM32F7:
https://www.st.com/resource/en/errata_s ... ronics.pdf from here
The chapter 3.11.1:
RTC calendar registers are not locked properly
Description
When reading the calendar registers with BYPSHAD = 0, the RTC_TR and RTC_DR registers may not be locked after reading the RTC_SSR register. This happens if the read operation is initiated one APB clock period before the shadow registers are updated. This can result in a non-consistency of the three registers. Similarly, the RTC_DR register can be updated after reading the RTC_TR register instead of being locked.
Workaround
Apply one of the following measures:
1.Use BYPSHAD = 1 mode (bypass shadow registers), or
2. If BYPSHAD = 0, read the RTC_SSR register again after reading the RTC_SSR, RTC_TR, RTC_DR registers to confirm that RTC_SSR is still the same, otherwise read the values again.
I did not see any measures in the driver to tackle this.
After the readout of CR in file os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c in line 657:
Code: Select all
cr = rtcp->rtc->CR;
...I would have expected something like this :
Code: Select all
#if defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
/* Handling of errata: Lock of shadow registers is not working properly
on some controllers*/
#if STM32_RTC_HAS_SUBSECONDS
if (rtcp->rtc->CR & RTC_CR_BYPSHAD == 0 && ssr != rtcp->rtc->SSR)
{
ssr = rtcp->rtc->SSR;
tr = rtcp->rtc->TR;
dr = rtcp->rtc->DR;
cr = rtcp->rtc->CR;
}
#endif /* STM32_RTC_HAS_SUBSECONDS */
#endif /* affected STM controllers */
Note: Also other STM32 controllers do have this errata. E.g.: STM32F427/437 and STM32F429/439 errata