In current stable branch (21.11.2) there is I2C v.1 driver and it has discrepancy with Reference Manual:
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"ChibiOS\os\hal\ports\STM32\LLD\I2Cv1\hal_i2c_lld.c"
...
252 static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
253 I2C_TypeDef *dp = i2cp->i2c;
254 uint32_t regSR2 = dp->SR2;
255 uint32_t event = dp->SR1;
...
But the Reference Manual for STM32F407 (for example) says:
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"Page 858 <27.6.6> DM00031020_RM0090_STM32F4xx.pdf
Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
This bit is cleared by software reading SR1 register followed reading SR2, or by hardware
when PE=0.
Thus, you must first read status register 1, then 2:
Code: Select all
252 static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
253 I2C_TypeDef *dp = i2cp->i2c;
254 uint32_t event = dp->SR1;
255 uint32_t regSR2 = dp->SR2;
...