- the PLL1 divider P must not be set to odd values. PLL2/3 divider P and PLL1/2/3 divider Q/R do not have this constrain.
- also add the missing dividers for RCC_CDCFGR1_CDCPRE_DIVx (64, 128, 256 and 512) aka STM32_CDCPRE_DIVx
Patch for the current ChibiOS trunk (-r15856):
RM0455 Rev9 on page 404 (section 8.7.11 RCC PLL1 dividers configuration register (RCC_PLL1DIVR)):
oh, i also think that STM32H7B0 should be included in the type3 selection of os/hal/ports/STM32/STM32H7xx/hal_lld.h:
Code: Select all
Index: external/ChibiOS/os/hal/ports/STM32/STM32H7xx/hal_lld.h
===================================================================
--- external/ChibiOS/os/hal/ports/STM32/STM32H7xx/hal_lld.h (revision 15856)
+++ external/ChibiOS/os/hal/ports/STM32/STM32H7xx/hal_lld.h (working copy)
@@ -154,7 +154,8 @@
defined(STM32H735xx) || defined(__DOXYGEN__)
#include "hal_lld_type2.h"
#elif defined(STM32H7A3xx) || defined(STM32H7B3xx) || \
- defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ)
+ defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || \
+ defined(STM32H7B0xx)
#include "hal_lld_type3.h"
#else
#include "hal_lld_type1.h"