FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P Topic is solved

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FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P  Topic is solved

Postby nikiwaibel » Thu Dec 08, 2022 2:05 pm

FIX to check PLL1 divider P properly on STM32H7A3/7B3/7B0 ("type3"):
  • the PLL1 divider P must not be set to odd values. PLL2/3 divider P and PLL1/2/3 divider Q/R do not have this constrain.
  • also add the missing dividers for RCC_CDCFGR1_CDCPRE_DIVx (64, 128, 256 and 512) aka STM32_CDCPRE_DIVx
(i've not read the reference manual for the other H7 types. maybe sthg like this should be added to type2/type1 as well …)

Patch for the current ChibiOS trunk (-r15856):
ChibiOS-PLL1_DIVP_CHECK-STM32H7.patch.gz
(569 Bytes) Downloaded 51 times


RM0455 Rev9 on page 404 (section 8.7.11 RCC PLL1 dividers configuration register (RCC_PLL1DIVR)):
swappy-20221208_134024.png


oh, i also think that STM32H7B0 should be included in the type3 selection of os/hal/ports/STM32/STM32H7xx/hal_lld.h:

Code: Select all

Index: external/ChibiOS/os/hal/ports/STM32/STM32H7xx/hal_lld.h
===================================================================
--- external/ChibiOS/os/hal/ports/STM32/STM32H7xx/hal_lld.h   (revision 15856)
+++ external/ChibiOS/os/hal/ports/STM32/STM32H7xx/hal_lld.h   (working copy)
@@ -154,7 +154,8 @@
     defined(STM32H735xx) || defined(__DOXYGEN__)
 #include "hal_lld_type2.h"
 #elif defined(STM32H7A3xx)  || defined(STM32H7B3xx)  ||                     \
-      defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ)
+      defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) ||                     \
+      defined(STM32H7B0xx)
 #include "hal_lld_type3.h"
 #else
 #include "hal_lld_type1.h"
but i've no board to test this…

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby Giovanni » Thu Dec 08, 2022 3:23 pm

Same, but adding that will not hurt.

Committed.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby nikiwaibel » Thu Dec 08, 2022 6:14 pm

hmm,

Code: Select all

(STM32_PLL1_DIVP_VALUE == 1)
should not be allowed, as far as i can see:
0000000: not allowed
0000001: pll1_p_ck = vco1_ck / 2 (default after reset)
0000010: not allowed
0000011: pll1_p_ck = vco1_ck / 4
...
1111111: pll1_p_ck = vco1_ck / 128
only 2, 4, 6, …, 128.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby Giovanni » Thu Dec 08, 2022 6:22 pm

You are right, it is documented that way, it is allowed on type2 but also works on type3, the demo uses 1 as value so the HW allows it.

I need to recalculate values in the demo to not use 1 then I will remove that.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby nikiwaibel » Thu Dec 08, 2022 8:08 pm

same happened to me. :-)

i think, if you write 0 to the PLL1-DIV-P register (a theoretical "/1"), it simply ignores it and stays at the current value (default = "/2" = register value 1).

in my case i was assuming 280 MHz clock (24 MHz / 15 * 175 / 1), but essentially it must have been 140 MHz (= 24 MHz / 15 * 175 / 2). i don't think that PLL1-DIV-2 has a "hidden feature" to do "/1" ;) now i am using 24 MHz / 3 * 70 / 2 = 280 MHz.

unfortunately i did not measure it using some hardware. i'll try again and run the benchmark … should be recognizable.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby nikiwaibel » Thu Dec 08, 2022 8:33 pm

intresting. on my board / MCU it looks like there is a hidden feature. :ugeek:

could it be a copy paste error in the reference manual (forgotten to overwrite the PLL1-DIV-P section)? :o

it is quite strange that this divider should be different from all the others … will try /3 and /5 :mrgreen:
Last edited by nikiwaibel on Thu Dec 08, 2022 8:59 pm, edited 1 time in total.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby nikiwaibel » Thu Dec 08, 2022 8:58 pm

/3 did not work for me (did not come up, maybe an exception some place), but /5 did!
* 24 / 3 * 70 / 2 = 280 (assuming testOslib results are 100%)
* 24 / 15 * 175 / 1 = "impossible" 280 --> seems to work as expected, about 100% performance (testOslib)
* 24 / 3 * 70 / 3 = "impossible" 187 --> did not work/boot
* 24 / 3 * 70 / 4 = 140 --> about 50% performance (testOslib)
* 24 / 3 * 70 / 5 = "impossible" 112 --> about 40% performance (testOslib)
strange. very strange.

i think i have to stop digging deeper into this rabbit-hole :)

i would implement it as written in the reference manual, but that decision that's up to you.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby Giovanni » Thu Dec 08, 2022 9:14 pm

Probably the divider is not generating 50% duty cycle square waves as clocks when using odd values, this is why those are forbidden (but actually possible).

Anyway, better follow the RM recommendations.

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Re: FIX for STM32H7A3/7B3/7B0 ("type3") to correctly check PLL1 divider P

Postby nikiwaibel » Fri Dec 09, 2022 1:52 am

i also can't make out these constrains from os/hal/ports/STM32/LLD/SDMMCv2/hal_sdc_lld.h

Code: Select all

#if STM32_HAS_SDMMC1 && (STM32_SDMMC1CLK * 10 > STM32_HCLK * 7)
#error "STM32_SDMMC1CLK must not exceed STM32_HCLK * 0.7"
#endif

#if STM32_HAS_SDMMC2 && (STM32_SDMMC2CLK * 10 > STM32_HCLK * 7)
#error "STM32_SDMMC2CLK must not exceed STM32_HCLK * 0.7"
#endif

#if !defined(STM32_SDMMC_MAXCLK)
#define STM32_SDMMC_MAXCLK              50000000
#endif


in the datasheet i can find this:
swappy-20221209_015020.png


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