Various issues with SDMMCv2 Topic is solved

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Various issues with SDMMCv2  Topic is solved

Postby andypiper » Sat Feb 11, 2023 2:14 pm

I have finally resolved all my issues with SDMMCv2. This is a summary of what I found, the patch we are using can be found at ... b6b579e67a

new link: ... bf195aafbd

1. There appears to be an issue with STM32_SDC_SDMMC_PWRSAV. I accidentally had this off (default is on) and I was getting DMA timeouts when teh card was being setup. These eventually resolved, but with it on there are no timeouts making me think there is a bug. In particular I am suspicious that perhaps the clock needs to be disabled when changing speeds.
2. CLKDIV is now 9 bits so the mask needs to be 0xFFFFFE00U
3. The changes to sdc_lld_read() and sdc_lld_write() with STM32_SDC_SDMMC_UNALIGNED_SUPPORT set means that blocks are always written in 512byte chunks, this turns out to be much slower than writing all at once which the old code allowed. I note that the old code still exists in SDIOv1.
4. __nocache_sd1_wbuf and __nocache_sd2_wbuf appear to be unecessary - the response is never used with DMA so no caching issues should occur.
5. MASK should be set inside the critical zone

I made some other changes related to DMA. I'm not totally sure whether they are strictly necessary, but the certainly work.

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