backup domain initialisation bug for H7

[alex31]

Hello,

H7 offers 4Ko of backup ram in addition to the 32 backups registers that are present on other MCU families.
For now, backup memory is lost when power is cut even is vbat is wired to a battery.
Backup regulator is enabled bia PWR_CR2_BREN bit, and one should wait that PWR_CR2_BRRDY is up to confirm that backup regulator is enabled.
As <Sigprof> has found on the discord channel (thanks to him), PWR_CR1_DBP must be set to authorize changing BREN value, and the order of setting these bits is inverted.

I propose a patch to fix backup memory persistence.

Alexandre

[anatolewilson]

Before enabling the backup regulator (BREN), you need to set the DBP (Disable Backup Domain Write Protection) bit.
After setting DBP, you can then set the BREN (Backup Regulator Enable) bit.
Here’s how you can do it programmatically (assuming you're writing in C or a similar language).

[Giovanni]

Before enabling the backup regulator (BREN), you need to set the DBP (Disable Backup Domain Write Protection) bit.
After setting DBP, you can then set the BREN (Backup Regulator Enable) bit.
Here’s how you can do it programmatically (assuming you're writing in C or a similar language).

Hi,

Is this about code on repository or the patch proposed by Alex31?

Giovanni

[FXCoder]

It is possible with the current (trunk) repository code to achieve the desired result via the setting in mcuconf.h

Code: Select all

#define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0  \
                                                            | PWR_CR1_DBP)
#define STM32_PWR_CR2                       (PWR_CR2_BREN | PWR_CR2_MONEN)


[nikiwaibel]

as of my knowledge, the 4k backup sram requires
* PWR->CR1 |= PWR_CR1_DBP_Msk; # disable backup protection
* PWR->CR2 |= PWR_CR2_BREN_Msk; # backup regulator enable
* while (!(PWR->CR2 & PWR_CR2_BRRDY_Msk)); # backup regulator ready

* i think the values stored in backup sram will not survive a reset (as the backup regulator is off after a reset??), but they may survive the sleep/suspend states.
* setting disable backup protection may not be required for reading, but enabling the BREN bit.
please correct me, if i am wrong!

the 32 backups registers (4 byte each) do NOT require the backup regulator. they can be read anytime. for writing, the backup protection needs to be disabled:
* PWR->CR1 |= PWR_CR1_DBP_Msk # disable backup protection

unfortunately, setting RCC->BDCR = RCC_BDCR_BDRST (which happens currently (r16597) in ChibiOS at os/hal/ports/STM32/STM32H7xx/hal_lld.c:66 aka stm32_clock_init() → init_bkp_domain()) clears the backup registers and possibly also the backup sram, as reported in viewtopic.php?f=35&t=6378.