I have a small suggestion for the makefiles that use the USE_VERBOSE_COMPILE flag from the project makefile.
Instead of explicitly checking the flag for each target rule like this:
Code: Select all
$(TCOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
ifeq ($(USE_VERBOSE_COMPILE),yes)
@echo
$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
else
@echo Compiling $(<F)
@$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
endif
We can just assign the output suppress character (@) to a variable at the top of the file, and use it each time:
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# Verbose flag
ifeq ($(USE_VERBOSE_COMPILE),yes)
Q=
NL="\n"Compiling
else
Q=@
NL=
endif
This simplifies the rules to something like this:
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$(TCOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
$(V)echo $(NL) $(<F)
$(V)$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
Maybe there is a good reason for keeping the if/else checks in place for every rule, but I think this is cleaner to read through. It's quite similar to a C preprocessor #define, which can really clean up and abstract away repetitive settings.
Is there a good reason to keep the explicit if/else checks in place for each target rule?
Thanks!