Backup SRAM

[talsit]

I'm trying to use the Backup SRAM, the one located in the Backup Domain, at 0x40024000, (BKPSRAM_BASE), and I'm quite confused about how to go about it. This is on a STM32F4 (custom board) with working RTC on backup battery (CR2032).

I see that hal_lld_init() calls hal_lld_backup_domain_init(), but nowhere does it enable the BKPSRAM, as specified in the Reference Manual (RM0090, Rev4), section 5.1.2, page 91, "Backup domain access". It says:

-Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register
-Set the DBP bit in the PWR power control register (PWR_CR)
-Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

The function hal_lld_init() enables the power interface by calling "rccEnablePWRInterface(FALSE);" then the function hal_lld_backup_domain_init() sets the DBP bit (PWR->CR |= PWR_CR_DBP;), but the BKPSRAMEN isn't set, and therefore all access to the BKPSRAM returns 0's. If I set that bit, but calling this:

RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;

Then I can access the contents and save things, and everything works across resets.

But if I remove main power, its contents are lost. The debugger shows all 0's again until I set the BKPSRAMEN bit, where the contents are again random values.

I'm also writing out data to the RTC->BKP0R registers - magic number, configuration version and checksum of the BKPSRAM contents, and those values are intact after power removal.

Any clue as to what is going on?

[Giovanni]

Hi,

Not sure, I never used it. Try to get barthess in IRC, he is more into the BD code.

Giovanni

[talsit]

So, barthess comes into the chat, I explain him my issue, says a couple of words and BINGO, solves my issue, indirectly. I had basically forgotten to enable the backup voltage regulator, and he told me that it probably needed a special hal init case, like RTC.

So now, with only these 5 lines at the end of hal_lld_backup_domain_init(), you too can have Vbat-backed SRAM:

Code: Select all

  /* Backup domain SRAM enable, and with it, the regulator */
  RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
  PWR->CSR |= PWR_CSR_BRE;
  while ((PWR->CSR & PWR_CSR_BRR) == 0)
    ;                                /* Waits until the regulator is stable */

Thanks!

[barthess]

@talsit
Thanks for you code. I will test it in my board and merge it in trunk.

[talsit]

Would you prefer a patch?