I2C implementation for STM32

[Giovanni]

I am sorry to hear that, hopefully somebody has some chips to donate. I will ask for some samples but I would not hold my breath.

Giovanni

[DrunkenDonkey]

barthess, can feel your pain, bulgaria was in same situation before, nothing worked from here

On the topic, can I request a small change in platforms/STM32/ic2_lld.c on line 282, getting constant warning in there because of missing braces, always makes me "oh shit" when I rebuild

[Badger]

Barthess, I have a spare F4 discovery, pm me your address and I'll send it your way! (assuming the postage isn't stupidly expensive) I think it is fair for all the i2c stuff you've done the board has an i2c device (accelerometer I think) so it should be a good dev platform

[drgnz]

I finally got this one going. It was a silly issue. Two questions:

1-Is the convention to give 8bit I2C addresses without shifting and assuming the last bit is 0/1 for r/w (say, 0x90 for the LM75 temp sensor), or to give 7bit unshifted addresses and have the API shift it (would be 0x48 for the same case)? The ST Micro example I had was using 0x90 but the ChibiOS code was shifting it by 1 bit so it wasn't working.

2- The code I have ignores the ACK options (they are turned on regardless). I imagine the intention is to turn this option later?

Regards.

[barthess]

Hi all.

DrunkenDonkey
Line 282 of my platforms/STM32/ic2_lld.c contain only

Code: Select all

break;

Provide more code around warning line.

Badger
I am glad to hear about it. The best dev platform is your own application borad, right? So I need only chip from this board and can carefully desolder it. Please, do NOT use express services like FedEx, DHL, etc. In my country they cause much problems and headaches. Use regular airmail instead. If you agree, than send it to the following address:

drgnz
1 - there is no 8bit API. 7bit notation used because datasheets contain it much often than 8bit. You can write simple wrapper if need 8bit.
2 - I am not understand your desire. Can you explain it in detail? Provide example?

Regards.

[Badger]

I suppose if you only want the chip it doesn't make sense for me to send the whole board! Do you have any particular STM32F2 in mind? Farnell has quite a few, is STM32F207VCT6 ok? I'll make a new order a the new few days, and posting a single chip should cost hardly anything. Or I could de-solder the F4 with my re-work station, and just send that, and build myself an F2-Discovery! Which would you prefer; F2 or F4? F4 could be sent sooner..

[barthess]

I prefer F4

[Badger]

Ok, I'll sort it out tonight and hopefully post tomorrow. I've made a note of your address so you can remove that from the forum now if you wish.

[DrunkenDonkey]

Barthess, this is the function in question:

Code: Select all

void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){
  I2C_TypeDef *dp = i2cp->id_i2c;

  switch(i2cp->flags & EV7_SUBEV_MASK) {

  case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS:
    /* Only for case of three bytes to be received.
     * DataN-2 and DataN-1 already received. */
    dp->CR1 &= (uint16_t)~I2C_CR1_ACK;  /* Clear ACK */
    *rxBuffp = dp->DR;                  /* Read the DataN-2. This clear the RXE & BFT flags and launch the DataN exception in the shift register (ending the SCL stretch) */
    rxBuffp++;
    chSysLockFromIsr();
    dp->CR1 |= I2C_CR1_STOP;            /* Program the STOP */
    *rxBuffp = dp->DR;                  /* Read the DataN-1 */
    chSysUnlockFromIsr();
    rxBuffp++;
    i2cp->rxbytes -= 2;                 /* Decrement the number of readed bytes */
    i2cp->flags = 0;
    dp->CR2 |= I2C_CR2_ITBUFEN;         /* ready for read DataN. Enable interrupt for next (and last) RxNE event*/
    break;

  case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS:
    /* only for case of two bytes to be received
     * DataN-1 and DataN are received */
    dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
    dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
    chSysLockFromIsr();
    dp->CR1 |= I2C_CR1_STOP;                    /* Program the STOP */
    *rxBuffp = dp->DR;                          /* Read the DataN-1*/
    rxBuffp++;
    *rxBuffp = dp->DR;                          /* Read the DataN*/
    chSysUnlockFromIsr();
    i2cp->rxbytes = 0;
    i2cp->flags = 0;
    _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */
    break;

  case I2C_FLG_MASTER_RECEIVER:
    /* Some times in hi load scenarions it is possible to "miss" interrupt
     * because STM32 I2C has OR'ed interrupt sources. This case handle that
     * scenario. */
    if (i2cp->rxbytes > 3){
      *rxBuffp = dp->DR;
      rxBuffp++;
      (i2cp->rxbytes)--;
    }
    else
>>> this line generates warning in eclipse/codesourcery G++      _i2c_unhandled_case(i2cp);
    break;

  default:
    _i2c_unhandled_case(i2cp);
    break;
  }
}

[barthess]

DrunkenDonkey
Fixed. Check out platforms/STM32/ic2_lld.c from rev.3453. I was not see that warning previously because I always compile with CH_DBG_ENABLE_ASSERTS TRUE.