Weird SPI3 stuff on STM32f103 when remapping

[fred]

Hi,

I've run into a strange issue when remapping some pins for the STM32f103ZET6 device.

The issue is as follows:

SPI3 uses PB3 and PB4 for CLK and MISO. In regular operation these pins function as JTDO and NJTRST resp. According to the datasheet I need to remap them by setting SWJ _CFG[2:0] to 010 or 100. This is JTAG-DP Disabled and SW-DP Enabled for 010 and JTAG-DP Disabled and SW-DP Disabled for 100.

The three SWJ_CFG bits are located in AFIO_MAPR.

So I do the following:
uint32_t temp = AFIO->MAPR;
temp |=AFIO_MAPR_SWJ_CFG_1;//set bit 25, SWJ _CFG[1]
temp &= ~(AFIO_MAPR_SWJ_CFG_0 | AFIO_MAPR_SWJ_CFG_2); //clear the other two
AFIO->MAPR = temp;

I flash the chip, start logic analyser, it resets and I look at the logic analyser output. I see massive activity on the SPI3 clock but then nothing (at the point where my own SPI3 code should generate clocks). I try again, and no change. The activity is due to the JTAG, which is correct, but my setting for SPI3 doesn't seem to take hold.

I look online and find a post where someone describes the same problem. The person found the solution: wipe the entire chip and reflash. This also works for me.

But now I look at the datasheet again and see that SWJ _CFG[2:0] is write-only. So just to check I write the contents of these registers to output (LCD) immediately after modifying AFIO->MAPR via chprintf:

temp = 0x2000000
AFIO->MAPR = 0x4000000

Eh?

SPI3 works, no complaints, but I'm left with these questions:

- Why do I need to wipe the entire device before this remapping takes on? Am I overlooking something related to the architecture?
- Why isn't my setting (temp) the same as the Mapping register?
- with SWJ_CFG in 100 I have "JTAG-DP Disabled and SW-DP Disabled" ... so ... how can I force it in 010 mode?

regards,
Fred