STM32L: Is there any reason why only use TIM2/3/4/9 in GPT?

[yushanh]

Hi all,

I'm using STM32L GPT driver and found that many timers are not used.

From the datasheet, we supposedly have 8 timers (2/3/4/9/10/11/6/7) plus 2 watchdogs.
However in "os/hal/platforms/STM32L1xx/stm32_isr.h", it only defines the handlers for TIM2/3/4/9.

Code: Select all

#define STM32_TIM2_HANDLER          TIM2_IRQHandler
#define STM32_TIM3_HANDLER          TIM3_IRQHandler
#define STM32_TIM4_HANDLER          TIM4_IRQHandler
#define STM32_TIM9_HANDLER          TIM9_IRQHandler

Is there any reason not using other timers for STM32L?

Also, from "os/hal/platforms/STM32/TIMv1/gpt_lld.c", TIM10 is not defined in the low level driver either.
Is it just because it wasn't supported for platforms other than STM32L?

Thanks.

[Giovanni]

The problem is that those timers are shared among 3 drivers: PWM, ICU, GPT and on some STM32s the IRQs are shared with other timers (TIM1 and TIM8 usually). To make the matter worse the sharing is not always the same on all STM32s.

This makes impossible to write a single ISR if the timers sharing it are assigned to two different drivers. All the unimplemented timers are those sharing IRQs with something else.

This could be addressed by creating a common TIM-ISR manager where the ISRs for all drivers would be located but we don't have that yet.

Giovanni