STM32 errata and port_switch

[king2]

Text from STM32F429 errata, 1.1:

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An interrupt occurring during the data-phase of a single word load to the stack pointer
(SP/R13) can cause an erroneous behavior of the device. In addition, returning from the
interrupt results in the load instruction being executed an additional time.
For all the instructions performing an update of the base register, the base register is
erroneously updated on each execution, resulting in the stack pointer being loaded from an
incorrect memory location.
The instructions affected by this limitation are the following:
• LDR SP, [Rn],#imm
• LDR SP, [Rn,#imm]!
• LDR SP, [Rn,#imm]
• LDR SP, [Rn]
• LDR SP, [Rn,Rm]

This is exactly what _port_switch does:

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ldr     sp, [r0, #CONTEXT_OFFSET]

There is a workaround:

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Replace LDR SP, [R0] by
LDR R2,[R0]
MOV SP,R2

Is this a problem or conditions mentioned in errata cannot be met in ChibiOS?

[Giovanni]

Hi,

I will look into this but that instruction is placed in code that is always executed with interrupts disabled.

Giovanni

[king2]

Ok,I just found this in errata and think that is is better to say about this than not to say.

[Giovanni]

Update:

The errata can only be triggered (in that point) on CM3 and CM4 devices when fast interrupts are used. Fast interrupts can preempt the kernel so interruption of that instruction is possible.

The code will be modified this way in next release:

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                .thumb_func
                .globl  _port_switch
_port_switch:
                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
                vpush   {s16-s31}
#endif

                str     sp, [r1, #CONTEXT_OFFSET]
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) &&                                \
    ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4))
                /* Workaround for ARM errata 752419, only applied if
                   condition exists for it to be triggered.*/
                ldr     r3, [r0, #CONTEXT_OFFSET]
                mov     sp, r3
#else
                ldr     sp, [r0, #CONTEXT_OFFSET]
#endif

#if CORTEX_USE_FPU
                vpop    {s16-s31}
#endif
                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}

Thanks for reporting.

Giovanni

[rew]

for reference:

Q: Why are you enabling the workaround for antique processors like F1xx when this is an F429 erratum?

A: The error is in the ARM processor, not in ST's implementation. NXP for example has documented the exact same erratum in THEIR ARM processors..