STM32F405RG clock and CAN configuration

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omcdr
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STM32F405RG clock and CAN configuration

Post by omcdr »

Hello All

I have STM32F405RG board with 8MHz xtal, I have problems with configure clock and CAN settings, I got errors:

Code: Select all

In file included from ../chibios/os/hal/include/hal.h:32:0,
                 from ../chibios/os/hal/src/hal.c:25:
../chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h:1140:2: error: #error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
 #error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
  ^
../chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h:1160:2: error: #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
 #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
  ^
../chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h:1239:2: error: #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
 #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
  ^
../chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h:1457:2: error: #error "invalid STM32_RTCPRE value specified"
 #error "invalid STM32_RTCPRE value specified"
  ^
../chibios/os/hal/ports/STM32/STM32F4xx/hal_lld.h:1467:2: error: #error "invalid STM32_RTCPRE value specified"
 #error "invalid STM32_RTCPRE value specified"
  ^
In file included from ../chibios/os/hal/include/can.h:103:0,
                 from ../chibios/os/hal/include/hal.h:48,
                 from ../chibios/os/hal/src/hal.c:25:
../chibios/os/hal/ports/STM32/LLD/CANv1/can_lld.h:128:2: error: #error "CAN1 not present in the selected device"
 #error "CAN1 not present in the selected device"
  ^
../chibios/os/hal/ports/STM32/LLD/CANv1/can_lld.h:132:2: error: #error "CAN2 not present in the selected device"
 #error "CAN2 not present in the selected device"
  ^
../chibios/os/hal/ports/STM32/LLD/CANv1/can_lld.h:331:3: error: unknown type name 'CAN_TypeDef'
   CAN_TypeDef               *can;


I have checked with STM32CubeMX: here and clock looks correctly.

Second problem is CAN, Ihave defined CAN but "not present in the selected device"

My configuration:
board.h

Code: Select all

#define BOARD_STM32F405
#define BOARD_NAME                  "STM32F405"

/*
 * Board oscillators-related settings.
 * NOTE: LSE not fitted.
 */
#if !defined(STM32_LSECLK)
#define STM32_LSECLK                0U
#endif

#if !defined(STM32_HSECLK)
#define STM32_HSECLK                8000000U
#endif

#define STM32F405xx


mcuconf.h

Code: Select all

#define STM32F4xx_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_HSE_ENABLED                   TRUE
#define STM32_LSE_ENABLED                   FALSE
#define STM32_CLOCK48_REQUIRED              TRUE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE                    4
#define STM32_PLLN_VALUE                    144
#define STM32_PLLP_VALUE                    2
#define STM32_PLLQ_VALUE                    6
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV4
#define STM32_PPRE2                         STM32_PPRE2_DIV2
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE                  1
#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE                 192
#define STM32_PLLI2SR_VALUE                 2
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE                 FALSE


/*
 * CAN driver system settings.
 */
#define STM32_CAN_USE_CAN1                  TRUE
#define STM32_CAN_USE_CAN2                  TRUE
#define STM32_CAN_CAN1_IRQ_PRIORITY         11
#define STM32_CAN_CAN2_IRQ_PRIORITY         11
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Giovanni
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Re: STM32F405RG clock and CAN configuration

Post by Giovanni »

Hi,

Take the mcuconf.h settings from a STM32F4-Discovery demo, it has the same frequencies. Those messages indicate clearly an error in the clock setup.

Not sure about the CAN issue, try recompiling after fixing mcuconf.h.

Giovanni
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Re: STM32F405RG clock and CAN configuration

Post by omcdr »

Mistake was in board.mk - wrong headers
Thank you for help.
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Re: STM32F405RG clock and CAN configuration

Post by omcdr »

I'm testing CAN example from F4 discovery on my board. I have configured gpio

Code: Select all

#define GPIOB_CAN1_RX                 8U 
#define GPIOB_CAN1_TX                 9U 

#define GPIOB_CAN2_RX                12U 
#define GPIOB_CAN2_TX                13U 

#define VAL_GPIOB_MODER              PIN_MODE_ALTERNATE(GPIOB_CAN1_RX) |       \
                                     PIN_MODE_ALTERNATE(GPIOB_CAN1_TX) |       \
                                     PIN_MODE_ALTERNATE(GPIOB_CAN2_RX) |       \
                                     PIN_MODE_ALTERNATE(GPIOB_CAN2_TX) |       

#define VAL_GPIOB_OTYPER             PIN_OTYPE_PUSHPULL(GPIOB_CAN1_RX) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOB_CAN1_TX) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOB_CAN2_RX) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOB_CAN2_TX) |       
                            
#define VAL_GPIOB_OSPEEDR           0xFFFFFFFF

#define VAL_GPIOB_PUPDR              PIN_PUPDR_FLOATING(GPIOB_CAN1_RX) |       \
                                     PIN_PUPDR_FLOATING(GPIOB_CAN1_TX) |       \
                                     PIN_PUPDR_FLOATING(GPIOB_CAN2_RX) |       \
                                     PIN_PUPDR_FLOATING(GPIOB_CAN2_TX) |       
                            
#define VAL_GPIOB_ODR               0xFFFFFFFF

#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_CAN1_RX, 9) |           \
                                     PIN_AFIO_AF(GPIOB_CAN1_TX, 9) |           \
                                     PIN_AFIO_AF(GPIOB_CAN2_RX, 9) |           \
                                     PIN_AFIO_AF(GPIOB_CAN2_TX, 9))


Can config is

Code: Select all

static const CANConfig cancfg500k_36Mhz = { 
CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP,
 CAN_BTR_SJW(0) | CAN_BTR_TS2(1) |  CAN_BTR_TS1(8) | CAN_BTR_BRP(5)};
};


I'm trying to send on CAN2 frame and I got error 0x510000 and second is 0x570000 in line

Code: Select all

errors |= chEvtGetAndClearFlags(&evCan2err);


What does mean this error ?
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Re: STM32F405RG clock and CAN configuration

Post by Giovanni »

Hi,

The lower 16 bits contain a mask of standard error bits:

Code: Select all

/**
 * @name    CAN status flags
 * @{
 */
/**
 * @brief   Errors rate warning.
 */
#define CAN_LIMIT_WARNING           1U
/**
 * @brief   Errors rate error.
 */
#define CAN_LIMIT_ERROR             2U
/**
 * @brief   Bus off condition reached.
 */
#define CAN_BUS_OFF_ERROR           4U
/**
 * @brief   Framing error of some kind on the CAN bus.
 */
#define CAN_FRAMING_ERROR           8U
/**
 * @brief   Overflow in receive queue.
 */
#define CAN_OVERFLOW_ERROR          16U
/** @} */


The upper 16 bits contain the error bits as specified in the CAN ESR register (not portable).

Code: Select all

  /**
   * @brief   A CAN bus error happened.
   * @note    The flags associated to the listeners will indicate that
   *          receive error(s) have occurred.
   * @note    In this implementation the upper 16 bits are filled with the
   *          unprocessed content of the ESR register.
   */
  event_source_t            error_event;


Giovanni
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Re: STM32F405RG clock and CAN configuration

Post by omcdr »

There is error in CAN_ESR TEC section:

Bits 23:16 TEC[7:0]: Least significant byte of the 9-bit transmit error counter
The implementing part of the fault confinement mechanism of the CAN protocol.


Could you verify my gpio settings, is correct ?
What can cause this error ?
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Re: STM32F405RG clock and CAN configuration

Post by Giovanni »

Are you generating board files using ChibiStudio or you modified board.h manually? the latter is not recommended.

Giovanni
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Re: STM32F405RG clock and CAN configuration

Post by omcdr »

I have used board.h from STM32F4-Discovery and manualy changed 4 pins for CAN1/2.
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Re: STM32F405RG clock and CAN configuration

Post by Giovanni »

PB9 is used on the board, probably that is your problem.

Giovanni
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Re: STM32F405RG clock and CAN configuration

Post by omcdr »

CAN is working, it was HW problem with standby pin.
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