Reset reason

[Tabulous]

yeah the RCC->CSR Reg has about 6 bits for reset reasons, but if cleared by RMVF bit on startup, the next reset should have the correct reason for reset.

[Giovanni]

Is it guaranteed that you find only one bit raised? Couldn't find this info.

Giovanni

[neums]

I've asked it there:

https://community.st.com/thread/35979-r ... on-stm32fx

waiting for response...

[neums]

Hi,
ST answered:
"It's possible in case of internal reset to have 2 Flag set in the same time."

[Giovanni]

So this API could just report "external reset" or "other reset" and a mask of platform-dependent flags, the RCC_CSR register in the STM32 case.

Giovanni

[neums]

May we wait for other replies at STMs page for some days.

[Tabulous]

if you poll the CRS register in this order, you will know you reason for reset. Yes NRST is always set as every reset work by pulling NRST low for afew micro seconds, but it should be the last bit you poll.

Code: Select all

    if( RCC->CSR & ( 1 << 31 ))
    {
        TGL_DEBUG( DBG_MASK_APP, "$ APP - RESET(PLWR)\r\n" );
    }
    else if( RCC->CSR & ( 1 << 30 ))
    {
        TGL_DEBUG( DBG_MASK_APP, "$ APP - RESET(WWDG)\r\n" );
    }
    else if( RCC->CSR & ( 1 << 29 ))
    {
        TGL_DEBUG( DBG_MASK_APP, "$ APP - RESET(IWDG)\r\n" );
    }
    else if( RCC->CSR & ( 1 << 28 ))
    {
        TGL_DEBUG( DBG_MASK_APP, "$ APP - RESET(SOFT)\r\n" );
    }
    else if( RCC->CSR & ( 1 << 27 ))
    {
        TGL_DEBUG( DBG_MASK_APP, "$ APP - RESET(POR)\r\n" );
    }
    else if( RCC->CSR & ( 1 << 26 ))
    {
        TGL_DEBUG( DBG_MASK_APP, "$ APP - RESET(NRST)\r\n" );
    }

Tested this and seems to work.

[Giovanni]

Moving topic.

Giovanni

[Giovanni]

bump

It will go in next HAL in a specific driver.

[electronic_eel]

Is there already any HAL code for this available that I could test?

I'm just working on a project where I need to check if the watchdog triggered a reset and alert the user that something went wrong.

Thanks.