RT-STM32F767ZI-NUCLEO144: invalid DMA stream associated to I2C4 (TX/RX) Topic is solved

[rasm]

If I enable I2C4 in the RT-STM32F767ZI-NUCLEO144 demo, I get the following error:

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In file included from ../../../os/hal/include/hal_i2c.h:85:0,
                 from ../../../os/hal/include/hal.h:135,
                 from ../../../os/hal/src/hal.c:25:
../../../os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.h:321:2: error: #error "invalid DMA stream associated to I2C4 RX"
 #error "invalid DMA stream associated to I2C4 RX"
  ^~~~~
../../../os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.h:327:2: error: #error "invalid DMA stream associated to I2C4 TX"
 #error "invalid DMA stream associated to I2C4 TX"
  ^~~~~
make: *** [../../../os/common/startup/ARMCMx/compilers/GCC/rules.mk:232: build/obj/hal.o] Error 1

It seems that the DMA channels for I2C4 are not valid. I haven't study this code and I'm not sure if this is valid, but if I change the DMA streams to the values in the attached patch the build error is gone.

[steved]

Two problems here:
1. The definitions in stm32_registry.h for the 32F767 are incomplete. This is what I calculated:

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#define STM32_HAS_I2C3                      TRUE
#define STM32_I2C3_EVENT_HANDLER            Vector160
#define STM32_I2C3_ERROR_HANDLER            Vector164
#define STM32_I2C3_EVENT_NUMBER             72
#define STM32_I2C3_ERROR_NUMBER             73
#define STM32_I2C3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 1) |\
                                             STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_I2C3_RX_DMA_CHN               0x00000310
#define STM32_I2C3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\
                                             STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_I2C3_TX_DMA_CHN               0x00030008

#define STM32_HAS_I2C4                      TRUE
#define STM32_I2C4_EVENT_HANDLER            Vector1BC
#define STM32_I2C4_ERROR_HANDLER            Vector1C0
#define STM32_I2C4_EVENT_NUMBER             95
#define STM32_I2C4_ERROR_NUMBER             96
#define STM32_I2C4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\
                                             STM32_DMA_STREAM_ID_MSK(1, 2) |\
                                             STM32_DMA_STREAM_ID_MSK(1, 1))
#define STM32_I2C4_RX_DMA_CHN               0x00200280
#define STM32_I2C4_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 6)
#define STM32_I2C4_TX_DMA_CHN               0x08000000

2. The default DMA channels ned changing in mcuconf.h:

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#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C4_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C4_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

I've just checked on a system which implements I2C1 and I2C4, and the above settings work for me.

[Giovanni]

Fixed as bug #920.

Giovanni