[possible BUG] Bug 458 might not be fixed completely Topic is solved

[Giovanni]

In the meanwhile I committed the fix as bug #592. You can just update from the repository.

Giovanni

[Giovanni]

Because an error the driver is not functional if assertions are disabled, it will be fixed in 3.0.0p5.

Giovanni

[shinelikerain]

The patch Giovanni proposed certainly improved SDIO writes, I am running at SDC_CLK_50MHz again.

I'll let the system run for a while and feedback if I encounter any issues.

Thank you!

[Giovanni]

Note that even if the card is recognized as 50MHz, the clock is always set to 25MHz, there is an STM32 errata preventing correct 50MHz operations.

Giovanni

[Koen]

Hello,
I discovered this bug fix while doing the F7 USB-MSD benchmarks. I then found the "SDIO clock divider BYPASS" errata in F205/F207/F215/F217/F40x/F41x but it isn't mentioned anymore in the F7 errata (and maybe others), so I removed it. Maybe a condition could be added based on the MCU family to restore the 50MHz bypass ?
Thank you, Koen

[Giovanni]

Hi,

Have you tested it on the F7?

Anyway, moving this topic in "bug reports".

Giovanni

[Koen]

Yes and I haven't noticed a problem. I also tried your test code on page 3. F765VIT6.

[Giovanni]

bump

[Giovanni]

I think this has been fixed already. If not, reopen it.

Giovanni

[Ceco]

Hello.

I'm using Chibios with STM32F437. This core is not affected by SD clock errata of older devices. Last days I made a lot of experiments with 48MHz SD clock - all seems fine for the moment. There is no such a issue in the errata sheet of the F437, too. The highest clock is important to achieve better performance.

So I think you can enable higher clock for F4 devices, or better include some macros to manipulate it on compile time.