chSysHalt (reason=0x8001918 "SV#8")

[0x3333]

I'm build a template project(For stm32f103), very minimal to bootstrap new projects.

Here is my main:

Code: Select all

#include "ch.h"
#include "hal.h"

#define LINE_ONBOARD_LED PAL_LINE(GPIOC, 13) // PC13

static void mainInit(void);

int main(void)
{
    // System initialization
    halInit();
    chSysInit();

    palSetLineMode(LINE_ONBOARD_LED, PAL_MODE_OUTPUT_OPENDRAIN);
    palClearLine(LINE_ONBOARD_LED);

    while (true)
    {
        palToggleLine(LINE_ONBOARD_LED);

        chThdSleepMilliseconds(100);
    }
}

If I enable CH_DBG_SYSTEM_STATE_CHECK, the program crashes, if disabled, works as expected:

Code: Select all

Temporary breakpoint 1, main () at ./src/main.c:30
30       halInit();
(gdb) n
n
31       chSysInit();
(gdb) n
30       halInit();
(gdb) n
31       chSysInit();
(gdb) n
38           palToggleLine(LINE_ONBOARD_LED);
(gdb) n
40           chThdSleepMilliseconds(100);
(gdb) n
^C
Program received signal SIGINT, Interrupt.
chSysHalt (reason=0x8001918 "SV#8") at ./lib/chibios/os/rt/src/chsys.c:213
213     }
(gdb) bt
#0  chSysHalt (reason=0x8001918 "SV#8") at ./lib/chibios/os/rt/src/chsys.c:213
#1  _dbg_check_enter_isr () at ./lib/chibios/os/rt/src/chdebug.c:204
#2  0x080013f0 in VectorB0 () at ./lib/chibios/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c:255
#3  <signal handler called>
#4  0x55555554 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)

What I'm doing wrong?

[Giovanni]

Probably you have problems with IRQ priorities, levels 0, 1 and 2 are reserved.

Giovanni

[0x3333]

Hi!
I don't believe so, I have nothing enabled, and none of the peripherals have priority lower than 3.

Code: Select all

/*
    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#ifndef MCUCONF_H
#define MCUCONF_H

#define STM32F103_MCUCONF

/*
 * STM32F103 drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1P5
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0

/*
 * IRQ system settings.
 */
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6

/*
 * ADC driver system settings.
 */
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_IRQ_PRIORITY 6

/*
 * CAN driver system settings.
 */
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7

/*
 * RTC driver system settings.
 */
#define STM32_RTC_IRQ_PRIORITY 15

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_USB1 FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14

/*
 * WDG driver system settings.
 */
#define STM32_WDG_USE_IWDG FALSE

#endif /* MCUCONF_H */

Thanks!

[Giovanni]

Are you using our startup files? have you enabled priority groups?

Giovanni

[0x3333]

Yes, stock. I'll upload the code to github so you can take a look, but it is pretty standard.

Thanks.

[0x3333]

Here it is: https://github.com/0x3333/stm32f1template

In the folder "lib/chibios", must have a copy of Chibios trunk, I omitted because I use a git submodule to initialize it.

[Giovanni]

Hi,

I see nothing obviously wrong but that error condition usually happens when some IRQ is able, somehow, to preempt a critical section. This can normally happen only when using priorities 0, 1 and 2 or after enabling the Cortex-M priority grouping without making the necessary settings in the port layer.

Giovanni

[0x3333]

Could this be a problem in the F1 port?

I'll take a look at the startup code, would you mind telling me where to look more closely?

Thanks

[Giovanni]

There is no F1 port, the startup code and the RTOS port code are the same for all devices.

In addition, the normal F1 demos work as intended.

Giovanni

[0x3333]

Sorry, I wrongly expressed myself, I meant, if this could be a problem with some F1 port code, like HAL, or something, because I'm doing pretty basic stuff, anyway, I'll take a look at the demo codes, see if this problem arises enabling CH_DBG_SYSTEM_STATE_CHECK in my bluepill.

I also have a spare F4, I'll try running on it. I'll post my results.

Thanks again.