Unround intermediate frequency in PLL calculation

[A319]

Hi,

I'm running with an external HSE of 26MHz on a STM32L4S5 and want to get to 78MHz. So I'm applying:

PLLM = 3
PLLN = 18
PLLR = 2

That will give me

SYSTICK_CK = ((((26000000U / 3) * 18) / 2) / 1)
OSAL_ST_FREQUENCY = 5000

However I'm getting this error:

Code: Select all

ChibiOS/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c:342:2: error: #error "the selected ST frequency is not obtainable because integer rounding"
 #error "the selected ST frequency is not obtainable because integer rounding"
  ^~~~~

This is true because (26000000U / 3) is no integer, hence SYSTICK_CK will be 77999994. Technically it should work because the intermediate frequency is used only in the PLL and cannot be accessed.

Note: I have changed the PLL values to different values, which work too.

Sven

[Giovanni]

Hi,

I don't see an easy fix for this except using float constants and calculations in the clock tree (very complex) and this could also introduce rounding errors.

Giovanni