Bug in STM32 hal_spi_v2_lld.c Topic is solved

[CsZoli]

Hi,

The bug exist in ChibiOS 21.11.2 at the following conditions
- Chibistudio 2022-01 with GCC 9.2.1.
- STM32F103
Bug visible when CPOL=1

on STM32 SPI clock line (SCK) is indefinit/tristate when SPI not enabled (SPE bit 0)
In the new v2 driver SPI is only enabled (SPE=1) during communication (spiexchange)
This cause incorrect operation as SPI clock line must be high when CS goes low (when CPOL=1).

My suggestion is to insert a spip->spi->CR1 |= SPI_CR1_SPE; at the end of spi_lld_start(SPIDriver *spip) function at row 216 in hal_spi_v2_lld.c:

/* SPI setup.*/
spi_lld_configure(spip);
spip->spi->CR1 |= SPI_CR1_SPE; // <- this line should added
return HAL_RET_SUCCESS;

With this mod clock line activated (goes high) after spiStart(...) so when spiSelect(..) pulls down CS line, start conditions are correct.

Regards
Zoltan

[Giovanni]

Hi,

Thanks for finding, the problem is clear, note that SPIv2 and SPIv3 keep SPE enabled so this only happens in SPIv1 (the one used by F1 devices).

The fix is not sufficient, SPE would be still disabled after the 1st transfer and the problem would happen again on successive ones. Will post an update before next release.

Giovanni

[Giovanni]

Hi,

I committed a fix on repository trunk, could you give it a try?

Giovanni

[CsZoli]

Hi Giovanni,

Yes, I can confirm it is working perfectly!
Also clock line remain high after transfer, as it should.
Thanks for your quick action!

Regards
Zoltan