SD on STM32H7

[joaquin]

I'm trying to migrate an aplication from a STM32F407 to the miniSTM32H7 board. Using the trunk version of Chibios, I have managed to migrate ADC and CAN, thanks to the examples on the "multi" directory.
However, I'm stuck with the SD driver and its use with Fatfs. Last problem is calling sdcConnect(), with caches disabled and SD clock at 80 MHz, almost at the end, when switching to high speed,it calls sdc_detect_bus_clk

Code: Select all

static bool detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) {

  if (SDC_MODE_CARDTYPE_MMC == (sdcp->cardmode & SDC_MODE_CARDTYPE_MASK)) {
    return mmc_detect_bus_clk(sdcp, clk);
  }
  return sdc_detect_bus_clk(sdcp, clk);
}

And then it fails on

Code: Select all

  /* Read switch functions' register.*/
  if (sdc_lld_read_special(sdcp, tmp, N, MMCSD_CMD_SWITCH, 0)) {
    return HAL_FAILED;
  }

I would really appreciatte if anyone could refer me to any working example that could guide me.

[Giovanni]

Hi,

FatFS is problematic with cache so you need to be careful. In trunk there is the demo /demos/STM32/RT-VFS-FATFS which includes a builder for the H735.

Note that the trick is hidden inside the FatFS VFS driver but basically is about prefixing with a "__nocache_" the FatFS structures, this makes the linker place them inside memory section made non-cacheable using MPU.

Giovanni

[joaquin]

Thanks a lot, Giovanni, I'll try it. This uC is giving me quite a lot of headaches!

[joaquin]

With the STM32/RT-VFS-FATFS, I adapted the board from the original STM32H735 to the STM32H743 I have in my board, with the minimum changes. It fails at exactly the same point:
- At sdcConnect(&SDCD1)...
- When it switches to high speed calling detect_bus_clk(sdcp, &clk)...
- It calls sdc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk), where clk=SDC_CLK_25MHz...
- At that function, when read switch functions' register, it calls sdc_lld_read_special con cmd=6, but when waiting for the transaction it fails

This happens at the initialization of SD Card, before calling any of FatFS routines, so probably changing structures of FatFS won't help, although I'll try it

[Giovanni]

Hi,

I just retested on my H735G-DK, it works. You should check GPIO settings then clock settings in your board files.

Giovanni

[joaquin]

Hi,
I just retested on my H735G-DK, it works. You should check GPIO settings then clock settings in your board files.
Giovanni

I have revisited every detail and clock configuration (my uC is a stm32h743 instead of an stm32h735, it requires changing clock settings) without success; with CubeMX generated code I can initialice the SD Card, but at FatFS mount it always fail.
I'm throwing in the towel, this CPU and its nightmare cache is too much, every step that on other CPUs are simple to develop, it takes ages to succeed on the H743 for me.
Anyway, thanks a lot for you support, Giovanni!!. Having succeed porting Chibios to H735 is really worthy of admiration

[Giovanni]

Are GPIO settings correct?

Giovanni

[joaquin]

Are GPIO settings correct?
Giovanni

I think so, as GPIO pins are the same on the STM32H743 and for STM32H735. As for PORTC (PD2 are identical to PC8..PC12):

Code: Select all

/*
 * GPIOC setup:
 *
 * PC0  - GPIOC_SPI1_CS2            (output pushpull).
 * PC1  - GPIOC_4_20mA_1            (analog).
 * PC2  - GPIOC_D_C                 (output pushpull).
 * PC3  - GPIOC_4_20mA_2            (analog).
 * PC4  - GPIOC_VPILOT              (analog).
 * PC5  - GPIOC_PIN5                (input pullup).
 * PC6  - GPIOC_DIO0                (input pullup).
 * PC7  - GPIOC_SENSOR4             (input pullup).
 * PC8  - GPIOC_SDMMC1_D0           (alternate 12).
 * PC9  - GPIOC_SDMMC1_D1           (alternate 12).
 * PC10 - GPIOC_SDMMC1_D2           (alternate 12).
 * PC11 - GPIOC_SDMMC1_D3           (alternate 12).
 * PC12 - GPIOC_SDMMC1_CK           (alternate 12).
 * PC13 - GPIOC_SW2                 (input pullup).
 * PC14 - GPIOC_OSC32_IN            (input floating).
 * PC15 - GPIOC_OSC32_OUT           (input floating).
 */
#define VAL_GPIOC_MODER             (PIN_MODE_OUTPUT(GPIOC_SPI1_CS2) |           \
                                     PIN_MODE_ANALOG(GPIOC_4_20mA_1) |   \
                                     PIN_MODE_INPUT(GPIOC_D_C) |           \
                                     PIN_MODE_ANALOG(GPIOC_4_20mA_2) |           \
                                     PIN_MODE_ANALOG(GPIOC_VPILOT) |  \
                                     PIN_MODE_INPUT(GPIOC_PIN5) |  \
                                     PIN_MODE_INPUT(GPIOC_DIO0) |           \
                                     PIN_MODE_INPUT(GPIOC_SENSOR4) |           \
                                     PIN_MODE_ALTERNATE(GPIOC_SDMMC1_D0) |           \
                                     PIN_MODE_ALTERNATE(GPIOC_SDMMC1_D1) |           \
                                     PIN_MODE_ALTERNATE(GPIOC_SDMMC1_D2) |          \
                                     PIN_MODE_ALTERNATE(GPIOC_SDMMC1_D3) |          \
                                     PIN_MODE_ALTERNATE(GPIOC_SDMMC1_CK) |          \
                                     PIN_MODE_INPUT(GPIOC_SW2) |         \
                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_SPI1_CS2) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_4_20mA_1) |   \
                                     PIN_OTYPE_PUSHPULL(GPIOC_D_C) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_4_20mA_2) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_VPILOT) |  \
                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |  \
                                     PIN_OTYPE_PUSHPULL(GPIOC_DIO0) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SENSOR4) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SDMMC1_D0) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SDMMC1_D1) |       \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SDMMC1_D2) |      \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SDMMC1_D3) |      \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SDMMC1_CK) |      \
                                     PIN_OTYPE_PUSHPULL(GPIOC_SW2) |     \
                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_SPI1_CS2) |       \
                                     PIN_OSPEED_HIGH(GPIOC_4_20mA_1) |      \
                                     PIN_OSPEED_HIGH(GPIOC_D_C) |       \
                                     PIN_OSPEED_HIGH(GPIOC_4_20mA_2) |       \
                                     PIN_OSPEED_HIGH(GPIOC_VPILOT) |     \
                                     PIN_OSPEED_HIGH(GPIOC_PIN5) |     \
                                     PIN_OSPEED_HIGH(GPIOC_DIO0) |       \
                                     PIN_OSPEED_HIGH(GPIOC_SENSOR4) |       \
                                     PIN_OSPEED_HIGH(GPIOC_SDMMC1_D0) |       \
                                     PIN_OSPEED_HIGH(GPIOC_SDMMC1_D1) |       \
                                     PIN_OSPEED_HIGH(GPIOC_SDMMC1_D2) |      \
                                     PIN_OSPEED_HIGH(GPIOC_SDMMC1_D3) |      \
                                     PIN_OSPEED_HIGH(GPIOC_SDMMC1_CK) |      \
                                     PIN_OSPEED_HIGH(GPIOC_SW2) |        \
                                     PIN_OSPEED_HIGH(GPIOC_OSC32_IN) |   \
                                     PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_SPI1_CS2) |         \
                                     PIN_PUPDR_FLOATING(GPIOC_4_20mA_1) |   \
                                     PIN_PUPDR_PULLUP(GPIOC_D_C) |         \
                                     PIN_PUPDR_FLOATING(GPIOC_4_20mA_2) |         \
                                     PIN_PUPDR_FLOATING(GPIOC_VPILOT) |  \
                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |  \
                                     PIN_PUPDR_PULLUP(GPIOC_DIO0) |         \
                                     PIN_PUPDR_PULLUP(GPIOC_SENSOR4) |         \
                                     PIN_PUPDR_FLOATING(GPIOC_SDMMC1_D0) |         \
                                     PIN_PUPDR_FLOATING(GPIOC_SDMMC1_D1) |         \
                                     PIN_PUPDR_FLOATING(GPIOC_SDMMC1_D2) |        \
                                     PIN_PUPDR_FLOATING(GPIOC_SDMMC1_D3) |        \
                                     PIN_PUPDR_FLOATING(GPIOC_SDMMC1_CK) |        \
                                     PIN_PUPDR_PULLUP(GPIOC_SW2) |     \
                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_SPI1_CS2) |             \
                                     PIN_ODR_HIGH(GPIOC_4_20mA_1) |         \
                                     PIN_ODR_HIGH(GPIOC_D_C) |             \
                                     PIN_ODR_HIGH(GPIOC_4_20mA_2) |             \
                                     PIN_ODR_HIGH(GPIOC_VPILOT) |        \
                                     PIN_ODR_HIGH(GPIOC_PIN5) |        \
                                     PIN_ODR_HIGH(GPIOC_DIO0) |             \
                                     PIN_ODR_HIGH(GPIOC_SENSOR4) |             \
                                     PIN_ODR_LOW(GPIOC_SDMMC1_D0) |             \
                                     PIN_ODR_LOW(GPIOC_SDMMC1_D1) |             \
                                     PIN_ODR_LOW(GPIOC_SDMMC1_D2) |            \
                                     PIN_ODR_LOW(GPIOC_SDMMC1_D3) |            \
                                     PIN_ODR_LOW(GPIOC_SDMMC1_CK) |            \
                                     PIN_ODR_HIGH(GPIOC_SW2) |           \
                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_SPI1_CS2, 0U) |          \
                                     PIN_AFIO_AF(GPIOC_4_20mA_1, 0U) |     \
                                     PIN_AFIO_AF(GPIOC_D_C, 0U) |          \
                                     PIN_AFIO_AF(GPIOC_4_20mA_2, 0U) |          \
                                     PIN_AFIO_AF(GPIOC_VPILOT, 0U) |    \
                                     PIN_AFIO_AF(GPIOC_PIN5, 0U) |    \
                                     PIN_AFIO_AF(GPIOC_DIO0, 0U) |          \
                                     PIN_AFIO_AF(GPIOC_SENSOR4, 0U))
#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_SDMMC1_D0, 12U) |          \
                                     PIN_AFIO_AF(GPIOC_SDMMC1_D1, 12U) |          \
                                     PIN_AFIO_AF(GPIOC_SDMMC1_D2, 12U) |         \
                                     PIN_AFIO_AF(GPIOC_SDMMC1_D3, 12U) |         \
                                     PIN_AFIO_AF(GPIOC_SDMMC1_CK, 12U) |         \
                                     PIN_AFIO_AF(GPIOC_SW2, 0U) |        \
                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) |      \
                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))

Code generated from STM32Cube also configured this values (I have also tested as PULLUP and PULLDOWN). One difference between Aliexpress boards and H735G-DK is that Aliexpress boards doesn't have voltage interface on SDIO pins.
I rather thinks it's a cache related problem, as I managed to initialice the AD Card using code from STM32Cube, but it fails on FatFS (both with Chibios included version and with STM32Cube). If I were able to completely avoid cache I could check it, but I don't know how to do it

Code: Select all

[Giovanni]

Try disabling the cache globally and see if it makes a difference.

The code is in crt1.c, comment out the likes 262 and 263.

Giovanni

[joaquin]

Try disabling the cache globally and see if it makes a difference.
The code is in crt1.c, comment out the likes 262 and 263.
Giovanni

I have rebuilt it from scratch, and now it seems that it initialices the card, although the reported capacity from the card is 16GB instead of the 8GB it actually has.
Regarding FatFS, I had to align FatFS buffer according to this note, otherwise it gives "FR_NO_FILESYSTEM" when mounting the card.
With this modification, FatFS doesn't throw any error, but it didn't work neither writing nor reading a file. Changing crt1.c didn´t help.