STM32F103Z, problems with FSMC and i2c

[mobyfab]

Check your ugfx board file and pin muxing.

It does not use DMA by default.

[alexblack]

Hi,

Alex how did you do this?
Like this?
AFIO->MAPR |= AFIO_MAPR_I2C1_REMAP

Yes.
From datasheet on STM32F103: PB7 is used by this functions: I2C1_SDA(8) / FSMC_NADV / TIM4_CH2(8).
Because You have problem with FSMC and I2C1 I suggested that may be this is your problem. Need to look FSMC setting to understand it.

[mukululul]

Hi Alex,
looks like you pointed me to major trace here, thanks!

I searched through the Spec STM32F103xE (Doc id 14611) and found that FSMC_NADV is not used in Mode 1 (Page 62).
Do you know what mode they are talking about there?
Is this the Channel?

In RM0008 I found this
---> snip (Doc ID 13902 Rev 14 Page 187)
Bit 10 FSMC_NADV: NADV connect/disconnect
This bit is set and cleared by software. It controls the use of the optional FSMC_NADV
signal.
0: The NADV signal is connected to the output (default)
1: The NADV signal is not connected. The I/O pin can be used by another peripheral
<--- snip
Sounds like I can switch off this bit and use the pin for i2c.
This brings out the question, who is configuring this bit? Is this configured by chibios by default?
Can I just change it before configuring FSMC or will chibios change the setting back during some device init?
What is the chibios way of handling this?
If chibios leaves this setting alone it might be a way to fix this, I will try this and post the result.

Many questions wainting for an answer

Thanks for all your help.

Michael

[Giovanni]

Hi,

The HAL does not touch the FSMC, all register values are those enforced after the reset.

Giovanni

[mukululul]

Hi Giovanni,
thank you for this helpful information. I am trying the following change right now:

I added this in my board init
AFIO->MAPR2|== AFIO_MAPR2_FSMC_NADV_REMAP;
compiling with the provided defines I get this:
../../boards/PowerMcuSTM32F103ZET/board.c:73:17: error: 'AFIO_MAPR2_FSMC_NADV_REMAP' undeclared (first use in this function)

I checked stm32f10x.h and found that for STM32F10X_HD no the register bit AFIO_MAPR2_FSMC_NADV_REMAP is not defined. It is only defined for STM32F10X_HD_VL and STM32F10X_XL.
The cortex I am using is a STM32F103ZET6 so my understanding sofar was that it is a cpu supported by the STM32F10X_HD define.
Am I wrong here or is the a define missing in the stm32f10x.h?

Thanks for all your help.

Regards
Michael

[mukululul]

Hi,
my lcd init now looks like this:

Code: Select all

static inline void init_board(GDisplay *g) {
   (void) g;
   rccDisableAHB(RCC_AHBENR_FSMCEN, 0);
#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)
   AFIO->MAPR2|= AFIO_MAPR2_FSMC_NADV_REMAP;

    /* set pin modes */
    IOBus busD = {GPIOD, 1|1<<1|1<<4|1<<5|1<<8|1<<9|1<<10|1<<14|1<<15, 0};
    IOBus busE = {GPIOE, 1<<6|1<<7|1<<8|1<<9|1<<10|1<<11|1<<12|1<<13|1<<14|1<<15, 0};
    palSetBusMode(&busD, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
    palSetBusMode(&busE, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
   palSetPadMode(GPIOA, GPIOA_TFT_LIGHT, PAL_MODE_OUTPUT_PUSHPULL);

   rccEnableAHB(RCC_AHBENR_FSMCEN, 0);

    const unsigned char FSMC_Bank = 3;

    /* Register Layout
     *
     * BTCR[0] = BCR[0]
     * BTCR[1] = BTR[0]
     * BTCR[2] = BCR[1]
     * BTCR[3] = BTR[1]
     * BTCR[4] = BCR[2]
     * BTCR[5] = BTR[2]
     * BTCR[6] = BCR[3]
     * BTCR[7] = BTR[3]
     *
     * Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4
    * Reset value: 0x0000 30DX
     * */

   /* FSMC timing */
   FSMC_Bank1->BTCR[(FSMC_Bank*2)+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
         | (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
         | (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;

   /* Bank1 NOR/SRAM control register configuration
    * This is actually not needed as already set by default after reset */
   FSMC_Bank1->BTCR[FSMC_Bank*2] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;

With bit 10 in AFIO_MAPR2 set I still have the problem that i2c wont work once FSMC is active.
Looks like there are more problems

Regards
Michael

[Tectu]

I took a look at the STM32F103 errata and there are two entries about issues with I2C1 pin remapping. However, I do not think that this applies to you (please give it a read anyways).


~ Tectu

[mukululul]

Hi Techu, bullseye!
In the Errata I found this

2.8.9 FSMC with I2C1 and TIM4_CH2
Description
When the FSMC is being used, the NADV signal is set to 1 by default when the alternate
function output is selected for this pin. TIM4_CH2 and the I2C1 SDA signal are in conflict
with the NADV signal.
Workaround
Do not use TIM4_CH2 as an output when the FSMC is being used.
Concerning I2C1, it is possible to use the remap functionality available on the PB8 and PB9
pins. Otherwise, disable the FSMC clock through the "RCC_AHBENR" register prior using
the I2C1.

This means I need to add a workaround which disables FSMC every time I want to use I2C or enable it only when needed.
Or a HW rework where I rewire I2C1 to P8/9 and rewire CAN from PB8/9 to PA11/12 and hope Uart1 wont mind using the unused CTS and RTS.
This FSCM attached LCD really kills the flexibility of the chip. Rewiring the LCD to a bitbanging interface would be another option but that would impact a lot of pins.
Looks like I need to design my own hardware first before doing the code.

I will try a code circumvention for now and let you know how it turned out.

Thanks for all your help.

Regards
Michael

[mukululul]

Hi,
here the promised result of the code circumvention:
After the FSCM init I turned off the clocks again.
then I added this:

Code: Select all

static inline void acquire_bus(GDisplay *g) {
   (void) g;
   rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
}

static inline void release_bus(GDisplay *g) {
   (void) g;
   rccDisableAHB(RCC_AHBENR_FSMCEN, 0);
}

This works at least for a prove of concept. I guess I need a mutex in addtion between i2c device accesses and the aquire/release bus functions to make it work for all cases.

Thanks to Tectu for the final hint which enabled me to make this work.
In order to find out if the first change is also needed I removed the

AFIO->MAPR2|= AFIO_MAPR2_FSMC_NADV_REMAP;

It turned out it is not needed, I did send data to the LCD in a loop and watched the data line of i2c, since it did not toggle I guess its fine when I do not change the setting for NADV.

Again thanks you all for your hints and help.

Regards
Michael

[Tectu]

Welcome, I'm glad that I could help.
The acquire_bus() and release_bus() routines seem to work as expected too I'm just curious about performance. How long would it take until the FSMC peripheral clock is stable?


~ Tectu