STM32F030C8T6 Clock Issue

[Tabulous]

I will assess and implement the changes however I will have to leave tests to you.

Giovanni

This is ok

[Tabulous]

Hi Giovanni
did anything happen on this ?

I will assess and implement the changes however I will have to leave tests to you.

Giovanni

This is ok

[Giovanni]

Weekend probably.

Giovanni

[Tabulous]

ive just pulled the latest down and i see you have added support for F030xC.

I've just tried this, there are some issues when building.

i.e. on F030xC USART3 there is no LIN, but the driver assumes all have LIN thus this creates a build error

Also the debuggiung does not work, its like the clock setup on F030xC is incorrect.

[Giovanni]

I added support for USART3..6 on F0.

Code: Select all

- HAL: Now STM32 USARTv2 driver initializes the ISR vectors statically on
       initialization. Disabling them was not necessary and added to
       the code size.
- HAL: Added serial driver support for USART 3..6 on STM32F030xC devices.

I had to modify the ISR initialization moving it into the init() function, this saved some code in the driver. If the change proves to not bring problems then I will extend it to the other drivers.

Giovanni

[Tabulous]

I added support for USART3..6 on F0.

Code: Select all

- HAL: Now STM32 USARTv2 driver initializes the ISR vectors statically on
       initialization. Disabling them was not necessary and added to
       the code size.
- HAL: Added serial driver support for USART 3..6 on STM32F030xC devices.

I had to modify the ISR initialization moving it into the init() function, this saved some code in the driver. If the change proves to not bring problems then I will extend it to the other drivers.

Giovanni

You have defined things twice how comes USART6 is using USART3 DMA ???

#define STM32_HAS_USART6 TRUE
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART3_RX_DMA_CHN 0x000D0D0D
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_USART3_TX_DMA_CHN 0x0000D0D0

[Giovanni]

Cut and paste.

Giovanni

[Giovanni]

I think the change to the clock tree for F030xC and F070 will take a while.

Giovanni

[Giovanni]

There must be some differences in RCC or clock tree.

Probably it is something simple but I don't have any HW for a debug session.

Giovanni

This is correct, the F0's have two different clock trees, this can be seen on the reference manual page 90/91

http://www.st.com/st-web-ui/static/acti ... 091010.pdf

if the device is Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices)
then the HSI has a fixed divide by 2, then PLL Mull x 12 to get 48Mhz

if the device is Clock tree (STM32F070x6, STM32F070xB and STM32F030xC)
then the HSI is divide by a selectable PREDIV, then PLL Mull to get 48Mhz

This is really hard to decide, see the documentation of PLLSRC about F0xx devices (RM0091), it says that PREDIV is forced to divide by 2 when HSI/2 is selected of those devices without the HSI:2 divider, it is like they are made SW-compatible with an HW trick.

I wonder if this is the same for 030/070 devices (RM0360), the thing is not mentioned but it could be done in the same way.

If this is true then the current code should work as-is. Could you verify? I have no devices with the 2nd clock tree.

Giovanni

[Tabulous]

There must be some differences in RCC or clock tree.

Probably it is something simple but I don't have any HW for a debug session.

Giovanni

This is correct, the F0's have two different clock trees, this can be seen on the reference manual page 90/91

http://www.st.com/st-web-ui/static/acti ... 091010.pdf

if the device is Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices)
then the HSI has a fixed divide by 2, then PLL Mull x 12 to get 48Mhz

if the device is Clock tree (STM32F070x6, STM32F070xB and STM32F030xC)
then the HSI is divide by a selectable PREDIV, then PLL Mull to get 48Mhz

This is really hard to decide, see the documentation of PLLSRC about F0xx devices (RM0091), it says that PREDIV is forced to divide by 2 when HSI/2 is selected of those devices without the HSI:2 divider, it is like they are made SW-compatible with an HW trick.

I wonder if this is the same for 030/070 devices (RM0360), the thing is not mentioned but it could be done in the same way.

If this is true then the current code should work as-is. Could you verify? I have no devices with the 2nd clock tree.

Giovanni

Sorry for the delay on this, just tried to enable PLL on a STM32F030CCT6 and it wont work, the device just keeps resetting

What board / processor did you create and test the port on ?