Re: External ADC & DMA
Posted: Mon Feb 06, 2017 3:30 pm
It looks that way.
Giovanni
Giovanni
Code: Select all
// CC1 channel is configured as input, IC1 is mapped on TI2
GPTD1.tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1);
// ADC Latch data on the falling edge of CLKOUT
GPTD1.tim->CCER |= STM32_TIM_CCER_CC1P; // CC1NP reset value is 0 -> falling edge (CC1NP/CC1P = b01)
// CC1 DMA request enabled
GPTD1.tim->DIER |= STM32_TIM_DIER_CC1DE;
// Capture enabled
GPTD1.tim->CCER |= STM32_TIM_CCER_CC1E;Code: Select all
uint16_t buffer[100];
// Allocate the stream (TIM1_CH2 --> Stream 6)
dmaStreamAllocate( STM32_DMA2_STREAM6, 0, NULL, NULL );
// Set the source Address
dmaStreamSetPeripheral( STM32_DMA2_STREAM6, GPIOB->IDR );
// Set the destination address
dmaStreamSetMemory0( STM32_DMA2_STREAM6, buffer );
// set the size of the output buffer
dmaStreamSetTransactionSize( STM32_DMA2_STREAM6, sizeof(buffer)*sizeof(buffer[0]) );
// config 16-bit HWORD transfers, peripheral to memory,
// fixed source address, inc dest address
// channel 0 is used, TIM1_CH2 @ Stream 6
dmaStreamSetMode( STM32_DMA2_STREAM6,
STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC |
STM32_DMA_CR_CHSEL(0));
dmaStreamSetFIFO(STM32_DMA2_STREAM6, 0);
dmaStreamEnable(STM32_DMA2_STREAM6);Code: Select all
dmaStreamSetPeripheral( STM32_DMA2_STREAM6, &GPIOB->IDR);Giovanni wrote:First verify if the timer is working as expected, I don't see it but I imagine you enabled its clock, you are the one with the debugger
Skadi wrote:I'm not able to attach a debugger. The controller is programmed by SWD.
Code: Select all
/* Initialize Timer for Reset mode (reset and starts the counter) */
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_TRIGGER;
sSlaveConfig.InputTrigger = TIMx_TS_TIxFPx;
sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_FALLING;
sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1;
sSlaveConfig.TriggerFilter = TIM_TRIG_FILTER;Code: Select all
// TIM1_CH2
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1));
// enable TIMER1 clock
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
// enable DMA2 clock
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
// 8 (ETP): External trigger polarity -> Falling Edge
// 6 (TS): Trigger selection: Input 2 (TI2FP2)
// 6 (SMS): Trigger Mode
TIM1->SMCR |= 0x8066;
// CC1 is mapped on TI2 -> input capture
TIM1->CCMR1 |= 0x0002;
// Polarity: falling edge
TIM1->CCER |= STM32_TIM_CCER_CC1P;
// CC1 capture enabled
TIM1->CCER |= STM32_TIM_CCER_CC1E;
// CC1 DMA request enabled
TIM1->DIER |= STM32_TIM_DIER_CC1DE;
Code: Select all
uint16_t buffer[100];
// Allocate the stream
dmaStreamAllocate( STM32_DMA2_STREAM2, 0, NULL, NULL );
// Set the source Address
dmaStreamSetPeripheral( STM32_DMA2_STREAM2, (uint16_t *)&(GPIOB->IDR));
// Set the destination address
dmaStreamSetMemory0( STM32_DMA2_STREAM2, (uint16_t *)&(buffer[0]));
// set the size of the output buffer
dmaStreamSetTransactionSize( STM32_DMA2_STREAM2, sizeof(buffer) );
// config 16-bit HWORD transfers, peripheral to memory,
// fixed source address, inc dest address
dmaStreamSetMode( STM32_DMA2_STREAM2,
STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC |
STM32_DMA_CR_CHSEL(6));
dmaStreamSetFIFO(STM32_DMA2_STREAM2, 0);
dmaStreamEnable(STM32_DMA2_STREAM2);
dmaWaitCompletion(STM32_DMA2_STREAM2);
dmaStreamDisable(STM32_DMA2_STREAM2);
dmaStreamRelease(STM32_DMA2_STREAM2);
// --> Transfer to computer