Half-Duplex burst mode DMAR

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rew
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Re: Half-Duplex burst mode DMAR

Post by rew »

alex31 wrote:
andypiper wrote: In the DSHOT protocol, each bit is coded with a signal with a fixed period and a positive pulse width which depend on the value of the bit.
I don't remember the exact value, but let's say that the period is 10µs, and positive width is 3µs for a 0 and 7µs for a 1 bit

To decode this, you just need to read the bit-value of the input 5 microseconds (in the non-real example timing) after the positive edge.

Set the counter to count off that 5 microseconds, trigger an interrupt when the timer finishes and read the databit.

If you want to do it all with DMA, you can DMA the input-data-register of the GPIO on the event of the timer finishing. Hmm. There might even be a timer mode that resets the timer on input event. In that case, a PWM compare event can be triggered a fixed amount of time later.

You''ll configure the DMA for bytes, meaning you get 8 times as much data than what you eventually can handle.
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