Hi,
I'm just trying out a 427 on my own board, the port is looking great so far, there are quite a lot of peripherals used on there so it should be good testing. I'm also looking forward to finding out whether the DCMI DMA errata is really fixed, which I should be able to do soon

I did notice that the .ld file for the 429 defines the whole DMA-able SRAM as one region "ram", whereas on the 407 this was mapped as separate "ram" and "ethram" regions for the 112KiB and 16KiB SRAM regions. One big region seems much more convenient, but I was wondering whether the SRAM can always be treated this way, for example for DMA transfers etc.?
I've been reading through the datasheet and reference manual, and I can't really find anything that seems relevant, except that the DMA controller apparently has separate bus connections for the 3 regions, not sure what the significance is, I guess putting buffers for use by different DMA controllers in different regions might help performance, but I'm not too bothered about this.
Ben.