[DONE] Starting ChibiOS on STM32F107 with Keil

[Maxxie]

I have solved problem with MAC<->PHY communication. The problem was in remapping RXD0, RDX1 and RXDV pins by USART3 according to initial Olimex board schematic.

Now I see coming packets on RMII interface by oscilloscope. CH_IRQ_HANDLER(ETH_IRQHandler) called only once during runtime. Both if (dmasr & ETH_DMASR_RS) and if (dmasr & ETH_DMASR_TS) triggered. One packet was transfered by MAC. And nothing more. What do you think?

[Giovanni]

Once the buffers are filled no more interrupts are be triggered until the frames are removed by the upper layer. Probably by placing the breakpoint the buffers get filled immediately while the CPU is stopped.

Giovanni

[Maxxie]

Once the buffers are filled no more interrupts are be triggered until the frames are removed by the upper layer. Probably by placing the breakpoint the buffers get filled immediately while the CPU is stopped.

Giovanni

I supposed that existing demo code process incoming frames. Because contain web server demo. Is not it?

[Maxxie]

Hi Giovanni,

Code: Select all

CH_IRQ_HANDLER(ETH_IRQHandler) {
  uint32_t dmasr;

  CH_IRQ_PROLOGUE();

  dmasr = ETH->DMASR;
  ETH->DMASR = dmasr; /* Clear status bits.*/

  if (dmasr & ETH_DMASR_RS) {
    /* Data Received.*/
    chSysLockFromIsr();
    chSemResetI(&ETHD1.rdsem, 0);
#if MAC_USE_EVENTS
    chEvtBroadcastI(&ETHD1.rdevent);
#endif
    chSysUnlockFromIsr();
  }

  if (dmasr & ETH_DMASR_TS) {
    /* Data Transmitted.*/
    chSysLockFromIsr();
    chSemResetI(&ETHD1.tdsem, 0);
    chSysUnlockFromIsr();
  }

  CH_IRQ_EPILOGUE();
}

Firstly you copy ETH->DMASR content to local variable and then same value write back to register. Why?

Is the upper notified by chSemResetI(&ETHD1.rdsem, 0) and chSemResetI(&ETHD1.tdsem, 0) or chEvtBroadcastI(&ETHD1.rdevent)? Can you please suggest any diagram or picture for clear understanding layers interwork between interrupt, stack and OS?

[Giovanni]

Hi,

Hi Giovanni,
Firstly you copy ETH->DMASR content to local variable and then same value write back to register. Why?

In order to clear the IRQ flags, only those served.

Is the upper notified by chSemResetI(&ETHD1.rdsem, 0) and chSemResetI(&ETHD1.tdsem, 0) or chEvtBroadcastI(&ETHD1.rdevent)? Can you please suggest any diagram or picture for clear understanding layers interwork between interrupt, stack and OS?

Both the event or the semaphore are used for synchronization for incoming frames (the event is optional), only the semaphore for transmitted frames. There are not many layers, the MAC driver offers a portable API over the underlying hardware, the upper stack only see the MAC driver and implements the remaining networking layers.

Giovanni

[Maxxie]

Is this correct form of RXDV falling edge? I can see this eight pulses constantly at falling edge. Is it defined by RMII?

[Maxxie]

I don`t what this pulses are but after configuring I/O pins Ethernet become works.

Why the maximum data payload for ping packets is 1472 bytes? What part of code define this limit? STM32 accept up to 8KB packets and contain 2KB FIFO buffer.

[Giovanni]

The frames size is limited to the maximum lenght for Ethernet frames, what is the need for larger frames? it would require changes to the driver anyway.

Giovanni

[Maxxie]

I need 1500 bytes according to max. Ethernet MTU. Excluding 8 bytes of ICMP header and 16 bytes IPv4 header it should be 1476 bytes for ICMP ping payload.

[Giovanni]

The frame size is set to 1522 which is the maximum. Probably it is because the IPv4 header is up to 20 bytes long.

Giovanni