[possible BUG] Bug 458 might not be fixed completely Topic is solved

[shinelikerain]

This seems to be related to the speed of the data clock.

If I override the switch to SDC_CLK_50MHz in sdcConnect() then writes to the card are working.

But what could be different between reads and writes at the higher clock rate

[Giovanni]

Is your card supposed to work at 50MHz?

Giovanni

[shinelikerain]

Hi Giovanni

sdc_detect_bus_clk() was reporting that it did but I will try some other cards.

But why are reads so different from writes?

[Giovanni]

I am having problems with this driver, blocks become unreadable after writing anything on them and remains unreadable until the card is reformatted on PC. Writes do not fail, just make the written block "broken".

I have to way to debug this driver, it has to be considered non functional for the time being.

Giovanni

[Badger]

Oh dear, I've just run into this problem as well. In my case, I can't even get sdcRead(&SDCD1, 0, buf, 1) to work; it fails in sdc_lld_wait_transaction_end() because of:

Code: Select all

if ((SDIO->STA & SDIO_STA_DATAEND) == 0)

I'm using a pixhawk board, and the original code works with this card without problem. Maybe there's an answer in there somewhere!

[Giovanni]

I wrote the following test code:

Code: Select all

    memset(buf, 0xAA, MMCSD_BLOCK_SIZE * 2);
    chprintf(chp, "Writing...");
    if(sdcWrite(&SDCD1, startblk, buf, 2)) {
      chprintf(chp, "failed\r\n");
      goto exittest;
    }
    chprintf(chp, "OK\r\n");

    memset(buf, 0x55, MMCSD_BLOCK_SIZE * 2);
    chprintf(chp, "Reading...");
    if (blkRead(&SDCD1, startblk, buf, 1)) {
      chprintf(chp, "failed\r\n");
      goto exittest;
    }
    chprintf(chp, "OK\r\n");

    for (i = 0; i < MMCSD_BLOCK_SIZE; i++)
      buf[i] = i;
    chprintf(chp, "Writing...");
    if(sdcWrite(&SDCD1, startblk, buf, 2)) {
      chprintf(chp, "failed\r\n");
      goto exittest;
    }
    chprintf(chp, "OK\r\n");

    memset(buf, 0, MMCSD_BLOCK_SIZE * 2);
    chprintf(chp, "Reading...");
    if (blkRead(&SDCD1, startblk, buf, 1)) {
      chprintf(chp, "failed\r\n");
      goto exittest;
    }
    chprintf(chp, "OK\r\n");

The first write works (writing a repetitive regular pattern), the first read works, the second write works (writing a complex pattern), the second read fails, the pattern is read back incorrectly, it is like it is skipping some bytes.
It could be a problem with specific cards, I will run more tests.

Giovanni

[Badger]

I've tried testhal/STM32/STM32F4xx/SDC unmodified on my Olimex board and experience the following:

Code: Select all

ch> sdc all
Connecting... OK

Card Info
CSD      : 400E0032 5B590000 1D6F7F80 0A4000A0
CID      : 27504853 44303447 30001800 4D00D1A8
Mode     :
Capacity : 3768MB
Single block aligned read performance:           2386 blocks/S, 1221632 bytes/S
16 sequential blocks aligned read performance:   17184 blocks/S, 8798208 bytes/S
Single block unaligned read performance:         2361 blocks/S, 1208832 bytes/S
16 sequential blocks unaligned read performance: 2640 blocks/S, 1351680 bytes/S
ch> sdc all
Connecting... OK

Card Info
CSD      : 400E0032 5B590000 1D6F7F80 0A4000A0
CID      : 27504853 44303447 30001800 4D00D1A8
Mode     :
Capacity : 3768MB
Single block aligned read performance:           1967 blocks/S, 1007104 bytes/S
16 sequential blocks aligned read performance:   15024 blocks/S, 7692288 bytes/S
Single block unaligned read performance:         1950 blocks/S, 998400 bytes/S
16 sequential blocks unaligned read performance: 2144 blocks/S, 1097728 bytes/S
sdcErase() test write failed

.

It looks like this matches your experiences. This happens with all the microSD cards I can find (all 4GB, mixture of verbatim and kingston).

If I revert to 7685 then the test works:

Code: Select all

ch> sdc all
Connecting... OK

Card Info
CSD      : 400E0032 5B590000 1D6F7F80 0A4000A0
CID      : 02544D53 41303447 1338A23F A800E156
Mode     :
Capacity : 3768MB
Single block aligned read performance:           1571 blocks/S, 804352 bytes/S
16 sequential blocks aligned read performance:   11712 blocks/S, 5996544 bytes/S
Single block unaligned read performance:         1562 blocks/S, 799744 bytes/S
16 sequential blocks unaligned read performance: 1680 blocks/S, 860160 bytes/S
ch> sdc all
Connecting... OK

Card Info
CSD      : 400E0032 5B590000 1D6F7F80 0A4000A0
CID      : 02544D53 41303447 1338A23F A800E156
Mode     :
Capacity : 3768MB
Single block aligned read performance:           1571 blocks/S, 804352 bytes/S
16 sequential blocks aligned read performance:   11712 blocks/S, 5996544 bytes/S
Single block unaligned read performance:         1562 blocks/S, 799744 bytes/S
16 sequential blocks unaligned read performance: 1680 blocks/S, 860160 bytes/S

[Giovanni]

The second log does not have the erase test, which is the one that fails.

After some digging, I found that the SDIO bus loses nibbles during the receive phase and then, of course, it fails because the bad CRC:

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  Address   0 - 3     4 - 7     8 - B     C - F               
  200014E0                      08090A0B  0CD0EF10          
  200014F0  11121314  15161718  191A1B1C  D1EF2021          
  20001500  22232425  26272829  2A2B2CD2  EF303132          
  20001510  33343536  3738393A  3B3C3DE3  F0414243          
  20001520  44454647  48494A4B  4C4D4E4F  50515253          
  20001530  54555657  58595A5B  5C5D5E5F  60616263          
  20001540  64656667  68696A6B  6C6D6E6F  70717273          
  20001550  74757677  78797A7B  7C7D7E7F  80818283          
  20001560  84858687  88898A8B  8C8D8E8F  90919293          

Note how some nibbles are missing, it looks like an HW issue more than a SW issue. Reducing the SDIO clock makes no difference apparently.

Giovanni

[Giovanni]

Apparently the problem (or one of the problems) is related to the 50MHz clock mode.

Change the code this way in order to disable it:

Code: Select all

void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {

  (void)sdcp;

  if (SDC_CLK_50MHz == clk) {
    SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS
                                             /*| SDIO_CLKCR_BYPASS*/;
  }
  else
    SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS;
}

The cause is an errata on the SDIO peripheral when the bypass option is set, if confirmed this would make the 50MHz mode intrinsically unreliable.

Please report if this change is helpful (or not).

Giovanni

[shinelikerain]

Thank you Giovanni,

I'll check this later this week.