Re: New STM32F0 devices (Cortex-M0)
Posted: Tue Jan 21, 2014 9:27 pm
Thanks. It seems I understood. I will try and if I will fail I will wait 
ChibiOS Web Boards
https://forum.chibios.org/
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*** ChibiOS/RT test suite
***
*** Kernel: 2.7.0unstable
*** Compiled: Jan 22 2014 - 14:05:49
*** Compiler: IAR
*** Architecture: ARMv6-M
*** Core Variant: Cortex-M0
*** Port Info: Preemption through NMI
*** Platform: STM32F051xx/F061xx Entry Level Medium Density devices
*** Test Board: TEST BOARD STM32F050
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--- Test Case 1.1 (Threads, enqueuing test #1)
--- Result: SUCCESS
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--- Test Case 1.2 (Threads, enqueuing test #2)
--- Result: SUCCESS
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--- Test Case 1.3 (Threads, priority change)
--- Result: SUCCESS
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--- Test Case 1.4 (Threads, delays)
--- Result: SUCCESS
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--- Test Case 2.1 (Semaphores, enqueuing)
--- Result: SUCCESS
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--- Test Case 2.2 (Semaphores, timeout)
--- Result: SUCCESS
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--- Test Case 2.3 (Semaphores, atomic signal-wait)
--- Result: SUCCESS
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--- Test Case 2.4 (Binary Semaphores, functionality)
--- Result: SUCCESS
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--- Test Case 3.1 (Mutexes, priority enqueuing test)
--- Result: SUCCESS
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--- Test Case 3.2 (Mutexes, priority return)
--- Result: SUCCESS
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--- Test Case 3.3 (Mutexes, status)
--- Result: SUCCESS
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--- Test Case 3.4 (CondVar, signal test)
--- Result: SUCCESS
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--- Test Case 3.5 (CondVar, broadcast test)
--- Result: SUCCESS
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--- Test Case 3.6 (CondVar, boost test)
--- Result: SUCCESS
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--- Test Case 4.1 (Messages, loop)
--- Result: SUCCESS
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--- Test Case 5.1 (Mailboxes, queuing and timeouts)
--- Result: SUCCESS
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--- Test Case 6.1 (Events, registration and dispatch)
--- Result: SUCCESS
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--- Test Case 6.2 (Events, wait and broadcast)
--- Result: SUCCESS
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--- Test Case 6.3 (Events, timeouts)
--- Result: SUCCESS
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--- Test Case 10.1 (Queues, input queues)
--- Result: SUCCESS
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--- Test Case 10.2 (Queues, output queues)
--- Result: SUCCESS
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--- Test Case 11.1 (Benchmark, messages #1)
--- Score : 129533 msgs/S, 259066 ctxswc/S
--- Result: SUCCESS
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--- Test Case 11.2 (Benchmark, messages #2)
--- Score : 106223 msgs/S, 212446 ctxswc/S
--- Result: SUCCESS
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--- Test Case 11.3 (Benchmark, messages #3)
--- Score : 106223 msgs/S, 212446 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
--- Score : 385840 ctxswc/S
--- Result: SUCCESS
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--- Test Case 11.5 (Benchmark, threads, full cycle)
--- Score : 85818 threads/S
--- Result: SUCCESS
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--- Test Case 11.6 (Benchmark, threads, create only)
--- Score : 113804 threads/S
--- Result: SUCCESS
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--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
--- Score : 32016 reschedules/S, 192096 ctxswc/S
--- Result: SUCCESS
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--- Test Case 11.8 (Benchmark, round robin context switching)
--- Score : 245440 ctxswc/S
--- Result: SUCCESS
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--- Test Case 11.9 (Benchmark, I/O Queues throughput)
--- Score : 418336 bytes/S
--- Result: SUCCESS
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--- Test Case 11.10 (Benchmark, virtual timers set/reset)
--- Score : 424850 timers/S
--- Result: SUCCESS
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--- Test Case 11.11 (Benchmark, semaphores wait/signal)
--- Score : 637264 wait+signal/S
--- Result: SUCCESS
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--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
--- Score : 464000 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
--- System: 396 bytes
--- Thread: 64 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- EventS: 4 bytes
--- EventL: 16 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- Queue : 36 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
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...
178 /*!< Interrupt Number Definition */
179 typedef enum IRQn
...
187 #if defined (STM32F0XX_MD)
188 /****** STM32F0XX_MD specific Interrupt Numbers ****************************************************/
...
201 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
...
218 #elif defined (STM32F0XX_LD)
219 /****** STM32F0XX_LD specific Interrupt Numbers *****************************************************/
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231 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
...
242 #elif defined (STM32F030)
243 /****** STM32F030 specific Interrupt Numbers ********************************************************/
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254 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
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157 /* The shared vector is initialized on driver initialization and never
158 disabled.*/
159 nvicEnableVector(ADC1_COMP_IRQn,
160 CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
...
Giovanni wrote:Ah understood, you just need to create the folder and those files taking them from another M0 device. I will add them if you are not in a hurry.
Giovanni